In this study, we construct the quantum reversible counterparts of the logical AND, OR, XOR, NOR, and NAND gates. We utilize a quantum Fourier transform (QFT)-based adder circuit that replicates the functionality of a digital half-adder, which computes the sum and carry of two input bits using XOR and AND gates, respectively. To realize different logic gate operations, we apply pre- and post-processing to the QFT-adder using quantum gates, leveraging Boolean algebra properties to enable conversions between various logical functions. Although the number of elementary quantum logic gates increases for a small number of inputs-making the approach appear inefficient at first glance-the overall required qubit count is reduced compared to non-QFT-based designs as the number of inputs increases.
In this study, we construct the quantum reversible counterparts of the logical AND, OR, XOR, NOR, and NAND gates. We utilize a quantum Fourier transform (QFT)-based adder circuit that replicates the functionality of a digital half-adder, which computes the sum and carry of two input bits using XOR and AND gates, respectively. To realize different logic gate operations, we apply pre- and post-processing to the QFT-adder using quantum gates, leveraging Boolean algebra properties to enable conversions between various logical functions. Although the number of elementary quantum logic gates increases for a small number of inputs-making the approach appear inefficient at first glance-the overall required qubit count is reduced compared to non-QFT-based designs as the number of inputs increases.
In this work, we develop quantum reversible counterparts of the logical AND, NAND, OR, NOR, and XOR gates within a single architectural template: a quantum Fourier transform (QFT)–based adder that emulates a digital half‐adder by computing the sum and carry of two input bits. Each member of the gate family is obtained from the same adder by inserting only X and SWAP gates as pre‐ and postprocessing steps, with the required Boolean identities supplied by De Morgan’s laws. We prove that every proposed circuit is unitary prior to readout, so the input data remain recoverable from the output state. The construction generalizes to N ‐input gates through an in‐place population‐count (Hamming‐weight) register, and we derive explicitly that the resulting qubit requirement is N + log 2 N , compared with the 2 N − 1 qubits of the standard Toffoli‐ladder synthesis; the derivation is validated by exhaustive simulation for N ≤ 8. We provide a comprehensive resource analysis‐qubit count, gate count, circuit depth, CX count, T count, transpiled depth, and success probability‐against Toffoli‐, CNOT‐, and X‐gate‐based reversible circuits as well as three multicontrolled‐NOT decompositions with different ancilla‐depth trade‐offs. The analysis shows that the qubit saving is obtained at the price of a larger two‐qubit‐gate count, and identifies the regimes in which the QFT‐based design is advantageous. All two‐input gates and a four‐input NAND instance are executed for every input combination on IBM quantum hardware and on a calibrated noise‐model simulator, and the measured outputs consistently reproduce the corresponding truth tables, with hardware success probabilities of 0.97–0.99 for the two‐input gates and 0.88–0.93 for the four‐input NAND.
Quantum computing necessitates the design of circuits via reversible logic gates. Efficient reversible circuit can be constructed by achieving low ancilla count, reducing logical depth and lowering Quantum costs. Generalized Peres gates have recently been realized with very low Quantum Cost (QC) by utilizing Quantum rotation gates. This is utilized in recent literature for efficient reversible circuit constructions for symmetric Boolean functions. In this paper, we extend this line of construction further by demonstrating efficient realization of adder circuits. In particular, we revisit the adder construction of Vedral, Barenco and Eckert to show that improvement of gate count and QC is achievable by exploiting a construction based only on Peres gates. We also report improved constructions of symmetric Boolean functions by following an approach recently proposed in the context of Boolean function complexity analysis.
Quantum computing is an emerging computational paradigm that represents and processes information using quantum states. This paper presents the implementation and simulation of a Quantum Half Adder using the IBM Qiskit framework. The proposed circuit performs one-bit binary addition and produces two outputs, SUM and CARRY, through reversible quantum operations. Classical input values are encoded into quantum states using Pauli-X gates. Controlled-NOT (CNOT) gates are used to realize the XOR relationship required for SUM generation, while a Toffoli (CCNOT) gate realizes the AND relationship required for CARRY generation. The complete design is implemented in Python and executed using the Qiskit Aer Simulator. Four possible input combinations are evaluated and the measured outputs are compared with the expected Half Adder truth table. Circuit visualization, terminal output, and measurement histograms are used to verify the operation. The results show that the simulated circuit produces the expected SUM and CARRY values for all input combinations. The work provides a simple practical model for understanding reversible quantum computation, quantum gates, and Qiskit-based quantum circuit simulation.
A quantum gate is the quantum analog of the classical logic gate of digital computers. It is a basic structural unit of a quantum circuit which operates on a small number of qubits to deliver a predefined output. A quantum circuit is a graphical representation of the sequence of the quantum gates used and the measurements performed in a quantum computation. Various quantum logic gates, namely, the Hadamard, T phase, NOT, Pauli-X, controlled NOT (CNOT), controlled-Z, SWAP and controlled phase gates as well as higher-level Toffoli and Fredkin gates are described. Conventions of reading quantum circuit diagrams are explained. Operation of a quantum full adder consisting of registers and gates is discussed, elaborating the role of the NOT gate, the sum calculation with CNOTgates and the carry C-out calculation with Toffoli gates. A primary tool used for performing arithmetic operations on a quantum computer is the quantum Fourier transform (QFT). The QFT adder and multiplier circuits are presented.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
The futuristic computing is desired to be more power full with low-power consumption.That is why quantum computing has been a key area of research for quite some time and is getting more and more attention.Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times.Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance.In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer.The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations.The quantum costs of these designs are comparable.Many of the implemented micro-operations are not seen in previous literatures.The performances of the proposed circuits are compared with existing designs wherever available.