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Physica Scripta

Hardware-efficient quantum arithmetic logic units for square lattice architectures

Junxu Li

Published Feb 27, 2026• 0 citations
Publisher

Abstract

Abstract Quantum arithmetic logic units (QALUs) are essential building blocks for quantum computation, yet their realization on near-term hardware is hindered by restricted qubit connectivity. Here we present hardware-efficient quantum arithmetic logic units (QALUs), including quantum adders, subtractors, multipliers, and dividers, for quantum computers with square lattice architectures. Our constructions rely solely on Pauli-X, CNOT, and controlled- X (CSX) gates, with all two-qubit operations confined to nearest-neitablghbor qubits. In addition, we introduce the quantum algorithm to obtain the two’s-complement representation of signed integers. These results demonstrate a scalable and hardware-efficient implementation of QALUs on square-grid quantum hardware, paving the way for more complex quantum algorithms on realistic devices.

DOI
10.1088/1402-4896/ae4b73

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Abstract Quantum arithmetic logic units (QALUs) are essential building blocks for quantum computation, yet their realization on near-term hardware is hindered by restricted qubit connectivity. Here we present hardware-efficient quantum arithmetic logic units (QALUs), including quantum adders, subtractors, multipliers, and dividers, for quantum computers with square lattice architectures. Our constructions rely solely on Pauli-X, CNOT, and controlled- X (CSX) gates, with all two-qubit operations confined to nearest-neitablghbor qubits. In addition, we introduce the quantum algorithm to obtain the two’s-complement representation of signed integers. These results demonstrate a scalable and hardware-efficient implementation of QALUs on square-grid quantum hardware, paving the way for more complex quantum algorithms on realistic devices.
Quantum arithmetic logic units (QALUs) constitute a fundamental component of quantum computing. However, the implementation of QALUs on near-term quantum computers remains a substantial challenge, largely due to the limited connectivity of qubits. In this paper, we propose feasible QALUs, including quantum binary adders, subtractors, multipliers, and dividers, which are designed for near-term quantum computers with qubits arranged in two-dimensional arrays. Additionally, we introduce a feasible quantum arithmetic operation to compute the two's complement representation of signed integers. The proposed QALUs utilize only Pauli-X gates, CNOT gates, and CXC\sqrt{X}CX​ (CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.
The design of arithmetic and logical unit is a crucial block schematic of quantum computing, which has gained popularity in recent years. While division is a successive subtraction, a logical multiplier employs the technique of successive addition, which are the essential blocks of the quantum computing. The key components including comparator design, adders, and subtractors are considered with the help of Quantum-Dot Cellular Automata (QCA) in this work. Such essential blocks of the Arithmetic Logic Unit (ALU) are designed, implemented, and tested in the simulation using QCADesigner version 2.0.3. The results are found to be appealing with the standard truth tables of the above logical circuits. Hence, the designs could be utilized in the practical applications of Internet of Things, Block chains and Cryptographic solutions catering to the challenges of industry, healthcare and finance sectors. Addressing challenges such as a reduced number of qubits and complexity reduction could make way for more robust and practical ALU designs in QCA-based quantum systems. In the proposed novel work, the number of qubits required has been reduced to 24, offering a notable reduction compared to several recent approaches. Hence, the novelty of the work lies in the architectural-level reorganization and logic-level minimization strategy, which collectively enable a significant reduction in design complexity (up to 93%) without introducing additional fabrication or simulation overhead, optimizing clock zone assignments to enhance timing efficiency.
Quantum arithmetic logic units (QALUs) perform essential arithmetic operations within a quantum framework, serving as the building blocks for more complex computations and algorithms in quantum computing. In this paper, we present an approach to prepare linear probability distributions with quantum full adders. There are three main steps. Firstly, Hadamard gates are applied to the two input terms, preparing them at quantum states corresponding to uniform distribution. Next, the two input terms are summed up by applying quantum full adder, and the output sum is treated as a signed integer under two's complement representation. By the end, additional phase -1 is introduced to the negative components. Additionally, we can discard either the positive or negative components with the assistance of the Repeat-Until-Success process. Our work demonstrates a viable approach to prepare linear probability distributions with quantum adders. The resulting state can serve as an intermediate step for subsequent quantum operations.
Quantum computing (Q-computing) is a revolutionary technology that applies quantum mechanics (QM) to implement calculations significantly quicker than traditional computers. Q-computing employs Q-bits (qubits) rather than classical bits, which can take on a superposition state, making it possible to represent both 0 and 1 at once. This distinctive property allows qubits to perform multiple calculations simultaneously, making Q computers exponentially more powerful as more qubits are added, compared to the linear scaling of classical computers. However, challenges such as qubit instability and error rates remain significant obstacles to fully realizing this potential. A vital aspect of this technology is the development of Q arithmetic circuits, which act as the foundational blocks for efficiently executing Q algorithms. Q half-adder and full-adder circuits are integral to performing fundamental arithmetic operations within Q computers. In contrast to classical adders, Q adders rely on Q gates such as Controlled NOT (CNOT) and Toffoli gates. These gates exploit Q phenomena like entanglement and superposition, allowing for more efficient computations. The Q half-adder consists of two qubits and adds two single bits, producing a carry and sum output. It utilizes the CNOT gate to compute the sum and the Toffoli gate (controlled-controlled-NOT [CCNOT]) to compute the carry. The Q full-adder builds on this, adding three qubits to produce a sum and a carry output, further increasing computational capacity. Through the entanglement of qubits, these circuits allow for more parallelism and speed compared to classical adders. Q carry-look-ahead adders (QCLAs) and Q ripple-carry adders (QRCAs) are used to perform more complex arithmetic operations based on these half-adder and full-adder structures. Q arithmetic circuits have broad applications, boosting secure key generation in cryptography, speeding up matrix operations for faster model training in machine learning, and enabling more precise, efficient image transformations in Q image processing, benefiting fields like medical imaging and computer vision.
Abstract This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two‐input and four‐input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform‐based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft‐core processor on a quantum processing unit.
In this paper, an n-bit Quantum Binary Adder-Subtractor (QBAS) is designed using quantum logic gates using IBM Qiskit. A comprehensive understanding of the principles of quantum computing and quantum logic gates is also provided. As the fundamental module of a binary adder-subtractor circuit is a full adder, various designs of quantum full adders (QFAs) from the literature are investigated on various aspects to deliberately choose the best quantum full adder suitable for QBAS application. A QBAS circuit is thus designed using the selected QFA, analyzed and tested for its ability to replicate the output of its classical counterpart. The results obtained here will aid researchers in the design of Quantum Arithmetic Logic Units (QALUs), Quantum multipliers, dividers, and other scalable adder circuits. The proposed circuits and its results shown here expected to pave the way for design of compact and state of the art quantum adders with reduced number of qubits, quantum cost.