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Progress in Superconductivity and Cryogenics

Timing analysis of RSFQ ALU circuit for the development of superconductive microprocessor

Kim J. Y, Seokhyeon Baek, S H Kim, J.H. Kang

Published Jan 1, 2005• 0 citations
OpenAlex

Abstract

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, , and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

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arXiv:1902.09500•IEEE Transactions on Applied Superconductivity•Mar 18, 2019•47 citations
We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, , and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.
As part of the effort to develop a superconductive microprocessor, we constructed a rapid single flux quantum (RSFQ) 4-bit arithmetic and logic unit (ALU) in a pipelined structure. To speed up the circuit, we used a forward clocking scheme. The 4-bit ALU consisted of ten RSFQ Half Adders, four 2 /spl times/ 2 switches, and several D flip-flops. By commutating output ports of the half adder, we were able to produce AND, OR, XOR, and ADD functions. The 4-bit ALU was fabricated using the Korea Photonics Technology Institute's ten-level 1.0 kA/cm/sup 2/ Nb process. The size of the ALU was 3.0 mm /spl times/ 1.5 mm, fitting in a 5 mm /spl times/ 5 mm chip. The fabricated 1-bit ALU block was successfully tested at up to a 40 GHz clock frequency. The complete 4-bit ALU operated correctly at up to a 5 GHz clock frequency.
We have designed, fabricated, and tested a rapid single flux quantum (RSFQ) 1 bit arithmetic logic unit (ALU) block. The circuit consists of three DC current driven SFQ switches and a half-adder. We successfully tested the half-adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half-adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached two switches at the input ports of the half-adder to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this set-up, the circuit was successfully tested up to 20 GHz. The chip was fabricated using a standard HYPRES 1 kA cm −2 Nb Josephson junction fabrication process.
This paper describes the design and testing of an 8-bit asynchronous wave-pipelined sparse-tree Rapid Single Flux Quantum (RSFQ) Arithmetic Logic Unit (ALU). Compared to previously developed RSFQ ALUs, this unit features an extensive set of 8 arithmetic and 12 logical operations. The execution of ALU operations consists of two steps. First, when necessary, one or both operands are inverted, and then operations are performed on these pre-processed data. Unlike the RSFQ Kogge-Stone-based designs, our parallel-prefix sparse-tree ALU has significantly reduced circuit complexity while maintaining robust operational margins at high frequency. An 8-bit ALU has been implemented with the International Superconductivity Technology Center (ISTEC) 10 kA/cm21.0 μm 9-metal ADP2.1 fabrication process as a joint effort between Stony Brook University, Yokohama National University, and Nagoya University. Using the CONNECT cell library and SFQ CAD tools developed at Nagoya and Yokohama, the Stony Brook team has developed a complete logical and physical design of the ALU chip. The 8-bit ALU core (without SFQ-to-dc and dc-to-SFQ converters) consists of 8832 Josephson junctions with an area of 7.2 mm2. Simulations show that the ALU can operate at the maximum rate of 42 GHz. It has the latency of 374 ps at a bias voltage of 2.5 mV. The chip was fabricated and tested at low frequency in 2012. Testing results showed malfunctioning of some gates but despite these shortcomings we still verified several ALU operations with the measured DC bias voltage margins of ±1.8%.
We have designed and demonstrated an arithmetic logic unit (ALU) based on rapid single-flux-quantum (RSFQ) technology. The ALU has been developed toward demonstration of high-performance information processing using a general purpose microprocessor CORE e4. The target operation frequency of the ALU is 50 GHz. In this paper, we present the design and high- speed functionality test results of the ALU. The ALU can execute 10 instructions. We aimed at high frequency operation with precise timing design using logic gates synchronized to the clock signal. The ALU contains 1555 Josephson junctions (JJs) and occupies a circuit area of 0.53mm2. We have demonstrated the correct operation of the ALU using on-chip high-speed test. The estimated maximum operating frequency based on measurement results is 80 GHz.
A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0-μm Nb/AlOx/Nb nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm2, and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of 3.09 × 1.66 mm2. It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of 6.25 × 10932-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any 4n-bit processing.
We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with an asynchronous instruction propagation provides the wave-pipeline operation of the ALU. The ALU instruction set consists of 14 arithmetical and logical instructions. It has been designed and simulated for operation up to a 10 GHz clock rate at the 10-kA/cm2fabrication process. The ALU is embedded into a shift-register-based high-frequency testbed with on-chip clock generator to allow for comprehensive high frequency testing for all possible operands. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with MIT Lincoln Lab's 10-kA/cm2SFQ5ee fabrication process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology. We evaluated the bias margins for all instructions and various operands at both low and high frequency clock. At low frequency, clock and all instruction propagation through ALU were observed with bias margins of +/-11% and +/-9%, respectively. Also at low speed, the ALU exhibited correct functionality for all arithmetical and logical instructions with +/-6% bias margins. We tested the 8-bit ALU for all instructions up to 2.8 GHz clock frequency.