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Review of Scientific Instruments

Time-deterministic and instruction-dynamic execution: A field-programmable gate array quantum-control processor

Xiaoqin Luo, Jiayun Song, Xiaolu Su

Published Oct 1, 2026• 0 citations
Publisher

Abstract

Long-running quantum computations, including error-corrected workloads, place joint demands on instruction availability, measurement-dependent control, and calibration updates. We present time-deterministic and instruction-dynamic execution, a field-programmable gate array (FPGA) quantum-control processor supporting runtime revision at both instruction and parameter levels. Dynamic Instruction Parameter Update (DIPU) supplies one-shot, next-match patches before parameter capture, while Dynamic Instruction Stream Overwrite (DISO) provides guarded replacement, logical deletion, and out-of-line insertion in eligible future regions of a resident program. A moving fetch-visibility guard coordinates instruction updates with execution, and event commitment isolates complete descriptors for independent hardware-timed dispatch. Revision applicability depends on update timing and execution progress; deterministic service applies to committed events under the stated scheduling conditions. The Xilinx ZCU102 implementation uses a 250-MHz control core and a 425-MHz timing/update domain. FPGA-resident measurements at the registered digital interfaces confirmed programmed-cycle dispatch for all tested descriptors committed at least one timing-domain cycle before their timestamps, with downstream ready and the stated first-in, first-out ordering conditions. Separate tests confirmed post-commit timestamp and payload invariance. The minimum all-success mapped DIPU margin was four control-domain cycles, and a replacement of L instruction words completed in L + 5 update-domain cycles under continuous payload delivery. Within the tested guard-distance range, rejected DISO requests reported an error and preserved the resident path, whereas all admitted revisions tested here executed complete revised sequences. These results provide a hardware execution basis for incorporating runtime-generated sequences and parameter corrections into precisely timed quantum computations with feedback.

DOI
10.1063/5.0356629

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Long-running quantum computations, including error-corrected workloads, place joint demands on instruction availability, measurement-dependent control, and calibration updates. We present time-deterministic and instruction-dynamic execution, a field-programmable gate array (FPGA) quantum-control processor supporting runtime revision at both instruction and parameter levels. Dynamic Instruction Parameter Update (DIPU) supplies one-shot, next-match patches before parameter capture, while Dynamic Instruction Stream Overwrite (DISO) provides guarded replacement, logical deletion, and out-of-line insertion in eligible future regions of a resident program. A moving fetch-visibility guard coordinates instruction updates with execution, and event commitment isolates complete descriptors for independent hardware-timed dispatch. Revision applicability depends on update timing and execution progress; deterministic service applies to committed events under the stated scheduling conditions. The Xilinx ZCU102 implementation uses a 250-MHz control core and a 425-MHz timing/update domain. FPGA-resident measurements at the registered digital interfaces confirmed programmed-cycle dispatch for all tested descriptors committed at least one timing-domain cycle before their timestamps, with downstream ready and the stated first-in, first-out ordering conditions. Separate tests confirmed post-commit timestamp and payload invariance. The minimum all-success mapped DIPU margin was four control-domain cycles, and a replacement of L instruction words completed in L + 5 update-domain cycles under continuous payload delivery. Within the tested guard-distance range, rejected DISO requests reported an error and preserved the resident path, whereas all admitted revisions tested here executed complete revised sequences. These results provide a hardware execution basis for incorporating runtime-generated sequences and parameter corrections into precisely timed quantum computations with feedback.
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Large-scale qubit systems represent the future of superconducting quantum computing. As the number of qubits and functions increases, the current qubit control architectures struggle to achieve large-scale expansion. To address this issue, we have developed a field-programmable gate array-based scheduling system, which serves as a control architecture deployed on measurement and control hardware. This system achieves the generation of multi-channel long sequence pulses using minimal storage space, with reusable envelope and instruction designs. The envelopes and instructions are preloaded into the electronics, with each instruction corresponding to a different segment of the output waveform. The architecture we designed allows for extended pulse control lengths and more complex experiments without the requirement for external storage resources. We present the resource utilization of the implementation and compare it with previous measurements under different qubit counts. To verify the functionality of the system, we conducted a series of performance tests and characterization experiments on the deployed electronics. The measured single-qubit relaxation time T1 is 34.1 μs, and the dephasing time T2* is 25.8 μs. We characterized the quality of the control pulses using a randomized benchmarking protocol, achieving an average fidelity of 99.962%.
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5 ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125 ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.
The Quantum Control Processor (QCP) bridges the gap between compiler toolchains and control electronics, and is responsible for translating compiled quantum circuits into executable instructions that directly manipulate qubits and handle measurement feedback. However, existing designs rely primarily on customized instruction sets, limiting design reuse and requiring significant effort to build supporting toolchains. Furthermore, efficiently addressing qubits and scheduling operations in highly scalable scenarios remains a critical challenge. In this work, we present a vectorized quantum control approach built upon the RISC-V Vector (RVV) engine with a quantum-oriented extension. Leveraging the high parallelism of RVV, our approach can address up to 128 qubits in a single instruction. We also embed parameterized rotation information into the instruction set, enabling dynamic tuning of gate rotations in hybrid quantum-classical programs. To support mid-circuit measurements, we design a hardware-based halt-resume protocol that resumes pipeline execution within 80 nsnsns of receiving the measurement result. Comprehensive evaluation using both RISC-V toolchains and FPGA prototypes demonstrates that our design achieves up to 2.52×\times× speedup over the baseline in program execution time, with excellent scalability.