Measurement-responsive quantum experiments require control programs that can revise future operations after execution has begun without disturbing events already committed to precise timing. We present Time-Deterministic and Instruction-Dynamic Execution (TIDE), an FPGA quantum-control processor that separates a runtime-revisable future from a hardware-timed committed-event stream. TIDE provides two complementary update paths: Dynamic Instruction Parameter Update (DIPU) applies a one-shot patch to the next matching event before parameter capture, while Dynamic Instruction Stream Overwrite (DISO) performs guarded replacement, logical deletion, and out-of-line insertion in future resident-program regions. Per-channel committed-event FIFOs isolate accepted descriptors from subsequent control-core and update activity. The implemented Xilinx ZCU102 design meets timing at 250 MHz for the control core and 425 MHz for the timing/update domain. With downstream ready, every tested descriptor committed at least one timing-domain cycle before its programmed timestamp was dispatched in the programmed cycle at the registered output interfaces. In separate post-commit tests, committed timestamps and payloads remained unchanged under the applied perturbations. The minimum all-success mapped DIPU margin was four 250 MHz control-domain cycles. Under continuous payload delivery, an L-word contiguous overwrite completed in L+5 update-domain cycles. Within the characterized guard-distance range, rejected DISO requests preserved the resident path, whereas all admitted replacement, deletion, and insertion transactions exercised here executed a complete revised sequence. TIDE therefore enables runtime adaptation of both parameters and instruction structure while preserving deterministic service of committed quantum-control events.
Measurement-responsive quantum experiments require control programs that can revise future operations after execution has begun without disturbing events already committed to precise timing. We present Time-Deterministic and Instruction-Dynamic Execution (TIDE), an FPGA quantum-control processor that separates a runtime-revisable future from a hardware-timed committed-event stream. TIDE provides two complementary update paths: Dynamic Instruction Parameter Update (DIPU) applies a one-shot patch to the next matching event before parameter capture, while Dynamic Instruction Stream Overwrite (DISO) performs guarded replacement, logical deletion, and out-of-line insertion in future resident-program regions. Per-channel committed-event FIFOs isolate accepted descriptors from subsequent control-core and update activity. The implemented Xilinx ZCU102 design meets timing at 250 MHz for the control core and 425 MHz for the timing/update domain. With downstream ready, every tested descriptor committed at least one timing-domain cycle before its programmed timestamp was dispatched in the programmed cycle at the registered output interfaces. In separate post-commit tests, committed timestamps and payloads remained unchanged under the applied perturbations. The minimum all-success mapped DIPU margin was four 250 MHz control-domain cycles. Under continuous payload delivery, an L-word contiguous overwrite completed in L+5 update-domain cycles. Within the characterized guard-distance range, rejected DISO requests preserved the resident path, whereas all admitted replacement, deletion, and insertion transactions exercised here executed a complete revised sequence. TIDE therefore enables runtime adaptation of both parameters and instruction structure while preserving deterministic service of committed quantum-control events.
Long-running quantum computations, including error-corrected workloads, place joint demands on instruction availability, measurement-dependent control, and calibration updates. We present time-deterministic and instruction-dynamic execution, a field-programmable gate array (FPGA) quantum-control processor supporting runtime revision at both instruction and parameter levels. Dynamic Instruction Parameter Update (DIPU) supplies one-shot, next-match patches before parameter capture, while Dynamic Instruction Stream Overwrite (DISO) provides guarded replacement, logical deletion, and out-of-line insertion in eligible future regions of a resident program. A moving fetch-visibility guard coordinates instruction updates with execution, and event commitment isolates complete descriptors for independent hardware-timed dispatch. Revision applicability depends on update timing and execution progress; deterministic service applies to committed events under the stated scheduling conditions. The Xilinx ZCU102 implementation uses a 250-MHz control core and a 425-MHz timing/update domain. FPGA-resident measurements at the registered digital interfaces confirmed programmed-cycle dispatch for all tested descriptors committed at least one timing-domain cycle before their timestamps, with downstream ready and the stated first-in, first-out ordering conditions. Separate tests confirmed post-commit timestamp and payload invariance. The minimum all-success mapped DIPU margin was four control-domain cycles, and a replacement of L instruction words completed in L + 5 update-domain cycles under continuous payload delivery. Within the tested guard-distance range, rejected DISO requests reported an error and preserved the resident path, whereas all admitted revisions tested here executed complete revised sequences. These results provide a hardware execution basis for incorporating runtime-generated sequences and parameter corrections into precisely timed quantum computations with feedback.
Scalable quantum processors require control, readout, feedback, calibration, and error correction to coexist under bounded latency and shared-resource constraints, whereas existing platforms typically optimize only a subset of these capabilities. This article presents QCORE (Quantum-Control-Oriented Real-Time Execution), a QPU-side digital control reference architecture positioned between the Host and a platform-specific analog/mixed-signal front end. QCORE separates task management, shared resources, hard-real-time execution, and long-timescale services into four hardware partitions. A fast-result sideband closes same-round feedback, a Measurement Packet provides a traceable measurement and service interface, and a common service-control skeleton, Tile-local QEC, and versioned safe-point commit organize calibration, error correction, and long-term state updates. Transaction-level, event-driven, and quantum-behavioral models are used for evaluation. At a background load of 0.8, the P99 latency of the shared Measurement Packet/Event feedback path is (1.984±0.004)Lmax. Closed-loop operation reduces the mean frequency error by 83.2%±0.8% and lowers the state-assignment error at maximum readout drift from 10.39%±0.54% to 5.37%±0.29%. No unsafe acceptance or mixed-version observation is observed in 100,000 configuration transactions, and Tile-local QEC reduces modeled global-boundary demand and yields a 2.08× capacity-normalized scaling estimate.
Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We present the development of an open-source FPGA (field-programmable gate array) based processor for pulse-level qubit control. Our processor is designed primarily as an upgrade to QubiC, an open source qubit control platform, but can also be adapted to other systems. The processor is distributed in nature, with one core per arbitrary waveform generator (AWG); simplifying the design and allowing for straightforward scaling. Each processor core implements an instruction set consisting of timed pulse commands as well as simple arithmetic and branching instructions. Our design also includes interfaces for synchronizing the different cores and requesting/receiving (optionally processed) measurement results. Together, these features will allow a user to program arbitrary control flow within a quantum circuit based on previous measurement results. In this poster, we detail our design along with the expected resource utilization on the Xilinx Virtex 7 FPGA, and present pulse-level simulations of our system in the context of a simple feedback experiment.
The Quantum Control Processor (QCP) bridges the gap between compiler toolchains and control electronics, and is responsible for translating compiled quantum circuits into executable instructions that directly manipulate qubits and handle measurement feedback. However, existing designs rely primarily on customized instruction sets, limiting design reuse and requiring significant effort to build supporting toolchains. Furthermore, efficiently addressing qubits and scheduling operations in highly scalable scenarios remains a critical challenge. In this work, we present a vectorized quantum control approach built upon the RISC-V Vector (RVV) engine with a quantum-oriented extension. Leveraging the high parallelism of RVV, our approach can address up to 128 qubits in a single instruction. We also embed parameterized rotation information into the instruction set, enabling dynamic tuning of gate rotations in hybrid quantum-classical programs. To support mid-circuit measurements, we design a hardware-based halt-resume protocol that resumes pipeline execution within 80 ns of receiving the measurement result. Comprehensive evaluation using both RISC-V toolchains and FPGA prototypes demonstrates that our design achieves up to 2.52× speedup over the baseline in program execution time, with excellent scalability.
Abstract Fault-tolerant quantum computing requires a classical control stack that can decode syndrome data within the coherence time of physical qubits. We address this requirement for a single-logical-qubit space-time repetition-code memory, treating the classical–quantum interface as a distributed real-time systems problem. The proposed architecture combines software Pauli frame tracking with a pipelined, streaming decoder mapped directly to FPGA hardware. Operating over a space-time syndrome graph, the system separates data-qubit errors from measurement ancilla faults. We evaluate Greedy, Minimum-Weight Perfect Matching (MWPM), and Union-Find (UF) decoders under a depolarizing noise model (effective bit-flip rate pX = 2p/3) with phenomenological measurement faults. A first Monte Carlo framework was implemented for distances d = 3, 5, and 7. Publication-grade threshold crossings were not obtained in the present shot budget; reported p_th figures below are literature-aligned design targets, not crossings measured in this work. Prior published comparisons motivate pth(MWPM) ≈ 10.4% and pth(UF) ≈ 9.6%, as an expected algorithmic penalty ∆ ≈ 0.8% that remains well within operational margins. A 400 MHz pipeline schedule targets deterministic execution between 170ns and 390ns at 400MHz on an AMD Zynq UltraScale+ RFSoC, satisfying sub-microsecond round-trip deadlines. Mitigation protocols for pipeline backpressure, queue overruns, and frame corruption are established to ensure deterministic runtime stability. Index Terms— quantum error correction, real-time systems, FPGA, Union-Find decoding, minimum-weight perfect matching, Pauli frame.
Large-scale qubit systems represent the future of superconducting quantum computing. As the number of qubits and functions increases, the current qubit control architectures struggle to achieve large-scale expansion. To address this issue, we have developed a field-programmable gate array-based scheduling system, which serves as a control architecture deployed on measurement and control hardware. This system achieves the generation of multi-channel long sequence pulses using minimal storage space, with reusable envelope and instruction designs. The envelopes and instructions are preloaded into the electronics, with each instruction corresponding to a different segment of the output waveform. The architecture we designed allows for extended pulse control lengths and more complex experiments without the requirement for external storage resources. We present the resource utilization of the implementation and compare it with previous measurements under different qubit counts. To verify the functionality of the system, we conducted a series of performance tests and characterization experiments on the deployed electronics. The measured single-qubit relaxation time T1 is 34.1 μs, and the dephasing time T2* is 25.8 μs. We characterized the quality of the control pulses using a randomized benchmarking protocol, achieving an average fidelity of 99.962%.