Real-Time Decoding Pipelines for a Space-Time Repetition-Code Quantum Memory: A Distributed Classical Control Architecture for Fault-Tolerant Operation
Abstract Fault-tolerant quantum computing requires a classical control stack that can decode syndrome data within the coherence time of physical qubits. We address this requirement for a single-logical-qubit space-time repetition-code memory, treating the classical–quantum interface as a distributed real-time systems problem. The proposed architecture combines software Pauli frame tracking with a pipelined, streaming decoder mapped directly to FPGA hardware. Operating over a space-time syndrome graph, the system separates data-qubit errors from measurement ancilla faults. We evaluate Greedy, Minimum-Weight Perfect Matching (MWPM), and Union-Find (UF) decoders under a depolarizing noise model (effective bit-flip rate pX = 2p/3) with phenomenological measurement faults. A first Monte Carlo framework was implemented for distances d = 3, 5, and 7. Publication-grade threshold crossings were not obtained in the present shot budget; reported p_th figures below are literature-aligned design targets, not crossings measured in this work. Prior published comparisons motivate pth(MWPM) ≈ 10.4% and pth(UF) ≈ 9.6%, as an expected algorithmic penalty ∆ ≈ 0.8% that remains well within operational margins. A 400 MHz pipeline schedule targets deterministic execution between 170ns and 390ns at 400MHz on an AMD Zynq UltraScale+ RFSoC, satisfying sub-microsecond round-trip deadlines. Mitigation protocols for pipeline backpressure, queue overruns, and frame corruption are established to ensure deterministic runtime stability. Index Terms— quantum error correction, real-time systems, FPGA, Union-Find decoding, minimum-weight perfect matching, Pauli frame.
Abstract Fault-tolerant quantum computing requires a classical control stack that can decode syndrome data within the coherence time of physical qubits. We address this requirement for a single-logical-qubit space-time repetition-code memory, treating the classical–quantum interface as a distributed real-time systems problem. The proposed architecture combines software Pauli frame tracking with a pipelined, streaming decoder mapped directly to FPGA hardware. Operating over a space-time syndrome graph, the system separates data-qubit errors from measurement ancilla faults. We evaluate Greedy, Minimum-Weight Perfect Matching (MWPM), and Union-Find (UF) decoders under a depolarizing noise model (effective bit-flip rate pX = 2p/3) with phenomenological measurement faults. A first Monte Carlo framework was implemented for distances d = 3, 5, and 7. Publication-grade threshold crossings were not obtained in the present shot budget; reported p_th figures below are literature-aligned design targets, not crossings measured in this work. Prior published comparisons motivate pth(MWPM) ≈ 10.4% and pth(UF) ≈ 9.6%, as an expected algorithmic penalty ∆ ≈ 0.8% that remains well within operational margins. A 400 MHz pipeline schedule targets deterministic execution between 170ns and 390ns at 400MHz on an AMD Zynq UltraScale+ RFSoC, satisfying sub-microsecond round-trip deadlines. Mitigation protocols for pipeline backpressure, queue overruns, and frame corruption are established to ensure deterministic runtime stability. Index Terms— quantum error correction, real-time systems, FPGA, Union-Find decoding, minimum-weight perfect matching, Pauli frame.
Abstract Quantum error correction (QEC) must eventually operate inside the real-timecontrol loop of a quantum processor, where a decoding decision must be avail-able within the coherence budget of the ancilla qubits—typically under onemicrosecond for superconducting devices. Software decoders running on CPUsor GPUs achieve throughputs of at most a few hundred thousand correctionsper second, which falls orders of magnitude short of this requirement. Thispaper presents a family of three monolithic QEC decoder kernels implementedin Vitis HLS and deployed on the Xilinx Alveo U55C FPGA: a 3-bit repetitioncode as a pedagogical warm-up, the full nine-qubit Shor [[9, 1, 3]] code, andthe seven-qubit Steane [[7, 1, 3]] CSS code. All three kernels operate exclusivelyover the AXI-Lite control bus—no high-bandwidth memory is required—andexecute as combinational pipelines with initiation interval II = 1 at 300 MHz,yielding 300 million corrections per second per compute unit. The Shor kerneluses a 256-entry BRAM-backed decoder look-up table (LUT), achieves an HLS-estimated critical-path delay of 2.318 ns against a 3.33 ns target, and consumes1 BRAM18K, 228 LUT6, 190 flip-flops, and zero DSPs in a single SLR. TheSteane kernel integrates three independently selectable decoder architectures inone kernel: a BRAM LUT, a combinational minimum-weight perfect matching(MWPM) solver, and a one-round union-find (UF) cluster decoder; its criticalpath is 1.941 ns. A complete software mirror of each hardware decoder, bit-exact with the FPGA output, is provided for host-side correctness verification.A 27/27 self-test against all single-qubit Pauli errors confirms the Shor decoder,and 21/21 confirms all three Steane decoder modes. Monte Carlo sweeps overthe single-Pauli and IID-depolarising error models, for 105 shots per point, showlogical error rates well below the break-even diagonal for both codes, with LUT,MWPM, and UF decoders producing statistically identical curves for the Steanecode under IID noise with p ≤ 0.10. The entire QEC pipeline, including syn-drome extraction and logical-error readout, fits in under 0.02% of the U55C’s user fabric, leaving the remaining capacity free for co-hosting the companion 30-qubit statevector simulator kernel or for replication of up to 20 identical QECcompute units on a single card.
Reliable large-scale quantum computation relies on fault-tolerant architectures, where quantum error correction (QEC) continuously extracts and decodes error syndromes in real time. A critical component in QEC is the decoder, a classical subsystem that must simultaneously deliver high logical accuracy and ultra-low latency. This paper presents a novel algorithm-hardware co-design that improves the accuracy-latency trade-off over existing approaches such as vanilla Minimum-Weight Perfect Matching (MWPM) and Union-Find (UF) decoders. At the algorithmic level, we introduce coset ensemble decoding, which improves UF decoding by explicitly exploiting logically equivalent cosets. Our method performs ensemble forest exploration to generate multiple coset-consistent candidates and aggregates them to approximate coset-level maximum-likelihood decoding. We further reduce computational and memory complexity via reverse-order elimination and lossless graph compression, without sacrificing accuracy. At the hardware level, we design a domain-specific architecture that temporally reuses resources, avoiding the code-distance-proportional resource growth in prior spatial architectures. Several optimizations, such as multi-bank memory hashing and hierarchical ID mapping, are proposed to mitigate pipeline stalls and memory conflicts under highly concurrent access patterns. Under a circuit-level depolarizing noise model, our co-design approach achieves a better accuracy-latency trade-off than prior MWPM- and UF-based decoders, while reducing FPGA LUT consumption by up to 8.2 times compared with reported UF-based decoder resources. The tunable candidate number further exposes a flexible design knob, enabling users to tailor decoding performance to the requirements of different fault-tolerant workloads. Our implementation is publicly available at https://github.com/IMSeonL/coset-ensemble-decoder.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.
Noise-induced errors in quantum information processing corrupt computation and cause useful algorithms to fail. Quantum ErrorCorrection (QEC) counteracts this by encoding a single logical qubit across many physical qubits and correcting errors through repeatedsyndrome measurements. The Minimum-Weight Perfect Matching (MWPM) decoder is the accuracy benchmark for surface-codedecoding, but its microsecond-scale latency can consume the entire QEC cycle time of superconducting processors, leaving almost nomargin for other control operations. Pre-decoded lookup tables reduce latency to the nanosecond scale, but their memory requirementsgrow exponentially with code size, limiting them to very small code distances. In this work, we demonstrate a single-level cache,implemented as a software prototype, that accelerates decoding by exploiting the repetitive nature of surface-code syndromes. Hitrates above 80% are achieved for code distances up to 9 at below-threshold noise rates, and effective decoding speedups of up to18.1 times over PyMatching’s standalone decoding time are observed at code distance ≥ 5. Cache lookup latency remains below 400nanoseconds in the worst case, with memory well below that of full lookup tables. We further develop a mathematical frameworkdefining the theoretical limits of any cache-based decoder.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration.
To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits.
Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 μs on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 μs per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.