Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2608.06875

QCORE: A Quantum-Control-Oriented Real-Time Execution Architecture with Extensible Closed-Loop Services and Shared AI Acceleration

Heyue Li, Yanshu Guo, Qichun Liu, Tiefu Li, Zhihua Wang, Hanjun Jiang

quant-phcs.ARSubmitted Aug 7, 2026• Announced Aug 10, 2026• 0 citations
arXivHTMLPDF

Abstract

Scalable quantum processors require control, readout, feedback, calibration, and error correction to coexist under bounded latency and shared-resource constraints, whereas existing platforms typically optimize only a subset of these capabilities. This article presents QCORE (Quantum-Control-Oriented Real-Time Execution), a QPU-side digital control reference architecture positioned between the Host and a platform-specific analog/mixed-signal front end. QCORE separates task management, shared resources, hard-real-time execution, and long-timescale services into four hardware partitions. A fast-result sideband closes same-round feedback, a Measurement Packet provides a traceable measurement and service interface, and a common service-control skeleton, Tile-local QEC, and versioned safe-point commit organize calibration, error correction, and long-term state updates. Transaction-level, event-driven, and quantum-behavioral models are used for evaluation. At a background load of 0.8, the $P_{99}$ latency of the shared Measurement Packet/Event feedback path is $(1.984\pm0.004)L_{\max}$. Closed-loop operation reduces the mean frequency error by $83.2\%\pm0.8\%$ and lowers the state-assignment error at maximum readout drift from $10.39\%\pm0.54\%$ to $5.37\%\pm0.29\%$. No unsafe acceptance or mixed-version observation is observed in 100,000 configuration transactions, and Tile-local QEC reduces modeled global-boundary demand and yields a $2.08\times$ capacity-normalized scaling estimate.

Comments
12 pages, 13 figures

Related papers

Real-Time Quantum Error Correction System Stack: Architecture, Algorithms, and Engineering Practice

Yaojian Chen, Chun-Yang Luan, Peilin Zheng +7 more

Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.

quant-pharXiv:2605.30765•Jun 1, 2026•0 citations

QMClaw: A Scalable General-purpose Framework for Quantum Measurement and Control

Zhiqiang Fan, Haoran He, Ping Lv +12 more

As quantum computing continues to scale, quantum measurement and control (QMC) are increasingly constrained by calibration workflow complexity and by requirements for low-latency execution, robust exception handling, and traceable workflow governance. Existing frameworks for QMC are specialized and task-specific, while language-model-based agents for QMC suffer from excessive latency and cannot satisfy the strict timing and control-density demands of large-scale quantum systems. Here we propose QMClaw, a general, workflow-oriented framework for QMC built, featuring a local-first, tool-governed, robust architecture. At its core is a RuleEngine-centered control layer that processes structured context, performs rule-based state transitions, and generates execution plans for typical calibration workflows. Language models are used only for natural-language interaction, high-level task understanding, and exception support, keeping the critical fast path efficient. We implement a single qubit tune-up workflow as a demonstration and validation using real quantum device dataset. We also prove that the framework achieves quantitatively acceptable levels in terms of resource cost, LLM calling times and decision latency, enabling its practical deployment in large-scale quantum qubit measurement and control scenarios. This work presents a general workflow-oriented framework for QMC and provides evidence that rule-centered architectures are a promising design choice for scalable quantum-system calibration.

quant-pharXiv:2609.04674•Sep 7, 2026•0 citations

A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency

Junyi Liu, Yi Lee, Yilun Xu +2 more

Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.

quant-pharXiv:2603.16203•Mar 18, 2026•0 citations

A Hardware-Accelerated Qubit Control System for Quantum Information Processing

Nizar Messaoudi, Clayton Crocker, Marc Almendros

In this paper we present a flexible, high-performance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.

Conference on Design of Circuits and Integrated Systems•Nov 18, 2020•6 citations

A Predictive Operating-System Control Layer for Quantum Computing Hardware and Execution Stacks

TADAYUKI NISHIMURA

Quantum processors exhibit time-varying hardwaredrift, environmental fluctuations, and correlated control errorsthat challenge reliable execution and increase the physical errorburden presented to higher-level error-correction procedures.Existing approaches address important aspects of quantumcalibration, feedback control, scheduling, and error correction,but these functions are typically studied and implemented asdistinct components. We introduce QID-OS (Quantum Intelligent Dynamic Operating System), an operating-system-levelcontrol-plane architecture for quantum execution that mediatesbetween physical hardware telemetry and higher-level compilation, runtime, and quantum error-correction services. QID-OSintegrates causal recursive least-squares (RLS) online parameterestimation, predictive pulse-level compensation, and adaptiveexecution scheduling within a closed-loop runtime architecture.The proposed framework is evaluated using a distance-3 surfacecode simulation under a specified non-Markovian noise model, afull-factorial 23 module ablation, and experiments on a 5-qubitconnected subset of an IBM Quantum superconducting processor.In simulation, QID-OS improves logical success probability overthe evaluated noise conditions, and the full configuration achievesthe highest success probability among the evaluated modulecombinations. On superconducting hardware, the experimentallyvalidated online RLS estimation and active pulse-compensationcomponents increase computational-basis success probabilityfrom 68.5% ± 0.4% to 88.4% ± 0.3% across three independent8-hour calibration windows, comprising 300 randomized testcircuits and 2,457,600 total measurement shots. These resultsdemonstrate the feasibility of using a predictive control-planearchitecture to mitigate hardware-level errors prior to higherlevel quantum error-correction processing.

•Oct 16, 2026•0 citations

Updated QubiC: Improved Scalability, Performance, and QPU Support

Gang Huang, Yilun Xu, Neelay Fruitwala +7 more

Quantum computers rely on classical computers for control and readout. In the NISQ era, quantum computers are increasing in scale and spanning a broader range of QPU architectures and experiment/algorithm design, requiring cost-effective and flexible control systems. QubiC, the open-source control system developed at Lawrence Berkeley National Laboratory, was designed to support quantum computers in this evolution. After a few developmental years, QubiC 1.0 demonstrated its control and measurement capabilities on a superconducting quantum processing unit (QPU). With growing requirements from the QPU, QubiC 2.0 was developed on the latest RFSoC platform with mid-circuit measurement and feed-forward features, along with a new AC analog front-end. The latest updates focus on performance — with hardware-efficient randomized compiling (RC) and hardware-assisted parameterized circuit execution —, scalability — with software capable of synchronizing multiple boards —, and supporting a broader range of superconducting QPUs with an AC and DC-coupled analog front-end.

IEEE International Conference on Quantum Computing and Engineering (QCE)•Sep 15, 2024•0 citations
Scalable quantum processors require control, readout, feedback, calibration, and error correction to coexist under bounded latency and shared-resource constraints, whereas existing platforms typically optimize only a subset of these capabilities. This article presents QCORE (Quantum-Control-Oriented Real-Time Execution), a QPU-side digital control reference architecture positioned between the Host and a platform-specific analog/mixed-signal front end. QCORE separates task management, shared resources, hard-real-time execution, and long-timescale services into four hardware partitions. A fast-result sideband closes same-round feedback, a Measurement Packet provides a traceable measurement and service interface, and a common service-control skeleton, Tile-local QEC, and versioned safe-point commit organize calibration, error correction, and long-term state updates. Transaction-level, event-driven, and quantum-behavioral models are used for evaluation. At a background load of 0.8, the P99P_{99}P99​ latency of the shared Measurement Packet/Event feedback path is (1.984±0.004)Lmax⁡(1.984\pm0.004)L_{\max}(1.984±0.004)Lmax​. Closed-loop operation reduces the mean frequency error by 83.2%±0.8%83.2\%\pm0.8\%83.2%±0.8% and lowers the state-assignment error at maximum readout drift from 10.39%±0.54%10.39\%\pm0.54\%10.39%±0.54% to 5.37%±0.29%5.37\%\pm0.29\%5.37%±0.29%. No unsafe acceptance or mixed-version observation is observed in 100,000 configuration transactions, and Tile-local QEC reduces modeled global-boundary demand and yields a 2.08×2.08\times2.08× capacity-normalized scaling estimate.
Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.
As quantum computing continues to scale, quantum measurement and control (QMC) are increasingly constrained by calibration workflow complexity and by requirements for low-latency execution, robust exception handling, and traceable workflow governance. Existing frameworks for QMC are specialized and task-specific, while language-model-based agents for QMC suffer from excessive latency and cannot satisfy the strict timing and control-density demands of large-scale quantum systems. Here we propose QMClaw, a general, workflow-oriented framework for QMC built, featuring a local-first, tool-governed, robust architecture. At its core is a RuleEngine-centered control layer that processes structured context, performs rule-based state transitions, and generates execution plans for typical calibration workflows. Language models are used only for natural-language interaction, high-level task understanding, and exception support, keeping the critical fast path efficient. We implement a single qubit tune-up workflow as a demonstration and validation using real quantum device dataset. We also prove that the framework achieves quantitatively acceptable levels in terms of resource cost, LLM calling times and decision latency, enabling its practical deployment in large-scale quantum qubit measurement and control scenarios. This work presents a general workflow-oriented framework for QMC and provides evidence that rule-centered architectures are a promising design choice for scalable quantum-system calibration.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
In this paper we present a flexible, high-performance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.
Quantum processors exhibit time-varying hardwaredrift, environmental fluctuations, and correlated control errorsthat challenge reliable execution and increase the physical errorburden presented to higher-level error-correction procedures.Existing approaches address important aspects of quantumcalibration, feedback control, scheduling, and error correction,but these functions are typically studied and implemented asdistinct components. We introduce QID-OS (Quantum Intelligent Dynamic Operating System), an operating-system-levelcontrol-plane architecture for quantum execution that mediatesbetween physical hardware telemetry and higher-level compilation, runtime, and quantum error-correction services. QID-OSintegrates causal recursive least-squares (RLS) online parameterestimation, predictive pulse-level compensation, and adaptiveexecution scheduling within a closed-loop runtime architecture.The proposed framework is evaluated using a distance-3 surfacecode simulation under a specified non-Markovian noise model, afull-factorial 23 module ablation, and experiments on a 5-qubitconnected subset of an IBM Quantum superconducting processor.In simulation, QID-OS improves logical success probability overthe evaluated noise conditions, and the full configuration achievesthe highest success probability among the evaluated modulecombinations. On superconducting hardware, the experimentallyvalidated online RLS estimation and active pulse-compensationcomponents increase computational-basis success probabilityfrom 68.5% ± 0.4% to 88.4% ± 0.3% across three independent8-hour calibration windows, comprising 300 randomized testcircuits and 2,457,600 total measurement shots. These resultsdemonstrate the feasibility of using a predictive control-planearchitecture to mitigate hardware-level errors prior to higherlevel quantum error-correction processing.
Quantum computers rely on classical computers for control and readout. In the NISQ era, quantum computers are increasing in scale and spanning a broader range of QPU architectures and experiment/algorithm design, requiring cost-effective and flexible control systems. QubiC, the open-source control system developed at Lawrence Berkeley National Laboratory, was designed to support quantum computers in this evolution. After a few developmental years, QubiC 1.0 demonstrated its control and measurement capabilities on a superconducting quantum processing unit (QPU). With growing requirements from the QPU, QubiC 2.0 was developed on the latest RFSoC platform with mid-circuit measurement and feed-forward features, along with a new AC analog front-end. The latest updates focus on performance — with hardware-efficient randomized compiling (RC) and hardware-assisted parameterized circuit execution —, scalability — with software capable of synchronizing multiple boards —, and supporting a broader range of superconducting QPUs with an AC and DC-coupled analog front-end.