Abstract Calibration summaries are used both to select physical qubits and to parameterize noisy emulators, creating a risk that agreement within a calibration-derived model is mistaken for validation on hardware. We test whether calibration-aware compiler rankings transfer to hardware using weighted-MaxCut instances implemented with the quantum approximate optimization algorithm. The evidence comprises four stages: 3240 historical calibration-derived simulations; a complete 54-pair hardware grid on three IBM Heron r2 processors; exact-circuit repeats 9.3–12.1 d later; and a contemporaneous five-arm refresh experiment. Full-calibration selection improves the median hardware approximation ratio by 0.74 percentage points (pp), with 29 resolved gains and 11 resolved losses. This is a mean-objective effect: its translation to exact-solution probability is instance- and size-dependent, and we do not extrapolate it beyond the tested n ⩽ 10 regime. A Qiskit Aer model constructed from the calibration state available before execution reproduced the direction of the measured full-calibration-versus-topology advantage in 35/54 comparisons, but systematically overestimated its size: the simulated advantage exceeded the subsequently measured hardware advantage by a median 1.35 pp. Regressing the measured hardware advantage on the simulated advantage gave a slope of 0.28 (workload-depth case-cluster 95% interval 0.06–0.52), rather than the unit slope of a calibrated predictor. The emulator identified the exact best of six backend-compiler configurations in only 5/18 cases (95% Wilson interval [0.125, 0.509]). By contrast, identical circuits preserved the compiler-effect sign in 16/18 later repeats ( r = 0.92 ). Refreshing the full-calibration mapping yielded a median +0.72 pp gain, whereas the calibration-score difference agreed in sign with the measured refresh benefit in only 9/18 cases. Calibration data are therefore useful for candidate discovery and timely refresh, but their scalar scores are not calibrated predictors of hardware performance or configuration ranking.
Abstract Calibration summaries are used both to select physical qubits and to parameterize noisy emulators, creating a risk that agreement within a calibration-derived model is mistaken for validation on hardware. We test whether calibration-aware compiler rankings transfer to hardware using weighted-MaxCut instances implemented with the quantum approximate optimization algorithm. The evidence comprises four stages: 3240 historical calibration-derived simulations; a complete 54-pair hardware grid on three IBM Heron r2 processors; exact-circuit repeats 9.3–12.1 d later; and a contemporaneous five-arm refresh experiment. Full-calibration selection improves the median hardware approximation ratio by 0.74 percentage points (pp), with 29 resolved gains and 11 resolved losses. This is a mean-objective effect: its translation to exact-solution probability is instance- and size-dependent, and we do not extrapolate it beyond the tested n ⩽ 10 regime. A Qiskit Aer model constructed from the calibration state available before execution reproduced the direction of the measured full-calibration-versus-topology advantage in 35/54 comparisons, but systematically overestimated its size: the simulated advantage exceeded the subsequently measured hardware advantage by a median 1.35 pp. Regressing the measured hardware advantage on the simulated advantage gave a slope of 0.28 (workload-depth case-cluster 95% interval 0.06–0.52), rather than the unit slope of a calibrated predictor. The emulator identified the exact best of six backend-compiler configurations in only 5/18 cases (95% Wilson interval [0.125, 0.509]). By contrast, identical circuits preserved the compiler-effect sign in 16/18 later repeats ( r = 0.92 ). Refreshing the full-calibration mapping yielded a median +0.72 pp gain, whereas the calibration-score difference agreed in sign with the measured refresh benefit in only 9/18 cases. Calibration data are therefore useful for candidate discovery and timely refresh, but their scalar scores are not calibrated predictors of hardware performance or configuration ranking.
Reliably executing quantum algorithms on noisy intermediate-scale quantum (NISQ) devices is challenging, as they are severely constrained and prone to errors. Efficient quantum circuit compilation techniques are therefore crucial for overcoming their limitations and dealing with their high error rates. These techniques consider the quantum hardware restrictions, such as the limited qubit connectivity, and perform some transformations to the original circuit that can be executed on a given quantum processor. Certain compilation methods use error information based on calibration data to further improve the success probability or the fidelity of the circuit to be run. However, it is uncertain to what extent incorporating calibration information in the compilation process can enhance the circuit performance. For instance, considering the most recent error data provided by vendors after calibrating the processor might not be functional enough as quantum systems are subject to drift, making the latest calibration data obsolete within minutes. In this paper, we explore how different usage of calibration data impacts the circuit fidelity, by using several compilation techniques and quantum processors (IBM Perth and Brisbane). To this aim, we implemented a framework that incorporates some of the state-of-the-art noise-aware and non-noise-aware compilation techniques and allows the user to perform fair comparisons under similar processor conditions. Our experiments yield valuable insights into the effects of noise-aware methodologies and the employment of calibration data. The main finding is that pre-processing historical calibration data can improve fidelity when real-time calibration data is not available due to factors such as cloud service latency and waiting queues between compilation and execution on the quantum backend.
Abstract A topology-driven suitability estimator answers whether a Max-Cut instance deserves quantum hardware. This paper asks the question that estimator cannot: does the answer change with the device? Extending the QSE framework from noiseless simulation to calibration-conditioned noise models of three IBM chip generations — Falcon (Guadalupe, cx), Eagle (Brisbane, ecr), and Heron (Torino, cz) — we evaluate depth-1 QAOA on 100 graphs from 12 structural families at N=10 and N=12, producing 300 physically valid (graph, device) evaluations. Three findings emerge. First, a negative baseline stronger than any in the noiseless literature: under calibrated noise, p=1 QAOA loses to a 15- ordering-averaged greedy heuristic on 300 of 300 instances (mean ratios 0.759 vs. 0.934), and even noiseless p=1 QAOA loses on all instances (0.803). Second, the degree of loss is predictable and device-dependent: a random forest reaches graph-grouped CV R2 = 0.431±0.086 from topology alone and 0.467±0.085 when calibration and transpilation features are added; a median-split relativeamenability classifier attains accuracy 0.77 and ROC-AUC 0.858 from topology alone, with average clustering the dominant signal (r = 0.56 with quantum utility). Third, a diagnostic negative result: a classifier asked to pick the better of the two modern backends per graph fails completely (AUC 0.434 vs. base rate 0.57) — and the failure is correct, because per-graph Torino–Brisbane differences sit at the shot-noise floor (paired t-test p = 0.03–0.07 across simulator seeds), whereas the Falcon–Eagle generation gap is decisive (p ≈ 10−28). A 4096-shot rerun confirms the diagnosis in both directions: the tie resolves (p = 2.5×10−11, Torino ahead by 0.004 in mean ratio) and the classifier rises to AUC 0.64 — a real but operationally minor ranking. Device-conditioning matters at the granularity of chip generations, not of individual healthy devices. An extension to the original 137-graph QSE benchmark at N=16 (411 further evaluations) confirms every finding and strengthens all learnability results (ratio R2 = 0.82; 1 amenability AUC 0.966; 0 QAOA wins in 711 total evaluations), and the full benchmark executed on three Heron R2 production devices (300 hardware evaluations, 94 s of QPU time) validates the study end-to-end: snapshot predictions hold at MAE ≤ 0.010, QAOA wins 0 of 1,221 evaluations overall, the amenability classifier transfers to hardware labels (AUC 0.827; 94% label agreement), and same-generation devices separate at 1024 shots (p ≤ 2.6 × 10−3) by an operationally minor 0.010. We also document how the greedy-gap hardness signal central to QSE collapses below N=16 (same-protocol RF R2 falls from 0.306 to 0.076; transitivity correlation from −0.564 to −0.351) — re-derivation on the original benchmark exposing a greedy-protocol difference that confounds naive cross-study comparisons — and two engineering failures — a ZZ-phase sign-convention bug caught by a cross-simulator parity check, and transpiler gatedirection faults in legacy Falcon noise models — whose diagnoses shaped the final pipeline.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
We evaluate calibration-based digital twins for IBM Quantum hardware, aiming to reproduce hardware measurement outcomes on classical simulators. We present a workflow that builds twins from downloadable calibration CSV files by mapping coherence times, gate and readout error rates, and operation durations to thermal-relaxation, depolarizing, and readout error channels, while reconstructing a directed coupling map to restore connectivity constraints during transpilation. We compare four twin variants (CSV-built, backend-derived simulator, backend-derived noise model, and fake-backend snapshots) under a common execution and validation protocol. Experiments on two IBM QPUs, ibm_brisbane and ibm_sherbrooke, use randomized five-qubit circuits of depths 10, 20, and 30 across four optimization levels. Weighted Jaccard similarity indicates that twins constructed from downloadable calibration CSV data often achieved the closest agreement with hardware, while backend-derived twins provided competitive and practical baselines. The results further show that agreement depends on both the target device and the transpilation settings, underscoring the need to validate digital twins for the specific execution setup rather than assuming transferability across devices.
UniMind is a user-space middleware for quantum-accelerated AI workloads that scores, places, executes, and refreshes calibration data in a closed loop. This record contains the v7 manuscript in two editions (12-page full and 6-page compact), each as compiled PDF and LaTeX source. The paper is a measurement study of how a quantum runtime should maintain scheduling decisions when hardware calibration changes over time. We instrument a 156-qubit superconducting device (ibm_marrakesh) across three primary daily snapshots (D0-D2, 2026-08-29 to 08-31) plus 34 hourly calibration snapshots (2026-09-01 to 09-02, three backends: marrakesh, kingston, fez). Four findings: (1) calibration validity is temporally bounded and small (day-over-day rank correlation 0.579, top-10 Jaccard 0.25, stale top-3 pins 1.94-2.1x worse across 24-34 h; hourly top-3 margins ~1e-3 vs median |dC| = 0.0127); we formalize the Calibration Validity Horizon T_valid as a lower-bound design primitive. (2) Adaptive refresh (top-10 Jaccard < 0.5 or dC > 0.005, ~0.04 ms per scoring pass) dominates static and periodic policies at near-zero cost; a 144-threshold sweep places the default at the Pareto knee. (3) Refresh, not placement selection, dominates end-to-end reliability at the measured scale (+33/37 pp with fresh pins; pinned vs free is a bounded null, 70.0% vs 76.7%, Fisher p = 0.77, MDE ~ 32 pp). (4) Proxy-trained layout models do not transfer: re-fitting the 7-dim utility J(G) on real device labels collapses its size out-of-sample Spearman from 0.818 to 0.13; feature ablation and a connectivity-vs-quality variance crossover at k ~ 100 isolate the mechanism. All experiments are open-source and reproducible from the companion repository; QPU job IDs and calibration snapshots are recorded in its data directory. Every claim traces to a recorded job or snapshot; a failed exploratory result (rank correlation 1.000 -> 0.771) is reported as unreplicated. The LLM-orchestration layer is a separable controlled-parameter reliability model, not a hardware claim.
Despite rapid progress in quantum optimization, broad real-hardware benchmarks comparing multiple algorithmic families across diverse combinatorial problems under a common protocol remain limited. We benchmark gate-based quantum optimization on four NP-hard problems: multi-dimensional knapsack (MDKP), maximum independent set (MIS), quadratic assignment (QAP), and market-share (MSP). We study VQE, CVaR-VQE, standard, multi-angle, and warm-start QAOA, together with qubit-efficient PCE and QRAO, on IBM Heron r1/r2 processors using resilience-level-2 mitigation. To our knowledge, this includes the first real-hardware QRAO results and the first multi-problem PCE hardware benchmark.
Across 247 method-instance combinations, we report transpiled circuit size, hardware outcomes, and an independent-error gate-count fidelity proxy, Fest. For MDKP and MIS, an empirical operating point near Fest≈0.1, corresponding to about 770 two-qubit gates at the median Heron-r2 CZ error rate, marks the onset of noise-dominated execution. QAP exposes a separate bottleneck: dense one-hot encodings and an exponentially sparse feasible manifold, with feasible fraction 10!/2100 at n=10; no tested hardware method produces a feasible assignment. Compiled QAOA-family circuits are generally noise dominated, and a matched uniform-random control shows that most feasible low-fidelity outcomes fall within the random range, apart from one finite-sample MIS warm-start exception. A SWAP-aware, fractional-gate, Nighthawk-topology compilation counterfactual reduces two-qubit counts but leaves all circuits below Fest=10−3. These conclusions apply to the tested implementations rather than QAOA in general. Qubit-efficient methods extend runnable instance sizes, but only within the empirical fidelity budget.