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arXiv:2603.14607

Evaluating Calibration-Based Digital Twins for IBM Quantum Hardware Simulation

Edgars Bautra, Maksims Dimitrijevs, Abuzer Yakaryilmaz

quant-phSubmitted Mar 15, 2026• Announced Mar 17, 2026• 0 citations
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Abstract

We evaluate calibration-based digital twins for IBM Quantum hardware, aiming to reproduce hardware measurement outcomes on classical simulators. We present a workflow that builds twins from downloadable calibration CSV files by mapping coherence times, gate and readout error rates, and operation durations to thermal-relaxation, depolarizing, and readout error channels, while reconstructing a directed coupling map to restore connectivity constraints during transpilation. We compare four twin variants (CSV-built, backend-derived simulator, backend-derived noise model, and fake-backend snapshots) under a common execution and validation protocol. Experiments on two IBM QPUs, ibm_brisbane and ibm_sherbrooke, use randomized five-qubit circuits of depths 10, 20, and 30 across four optimization levels. Weighted Jaccard similarity indicates that twins constructed from downloadable calibration CSV data often achieved the closest agreement with hardware, while backend-derived twins provided competitive and practical baselines. The results further show that agreement depends on both the target device and the transpilation settings, underscoring the need to validate digital twins for the specific execution setup rather than assuming transferability across devices.

Comments
16 pages, 1 figure

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We evaluate calibration-based digital twins for IBM Quantum hardware, aiming to reproduce hardware measurement outcomes on classical simulators. We present a workflow that builds twins from downloadable calibration CSV files by mapping coherence times, gate and readout error rates, and operation durations to thermal-relaxation, depolarizing, and readout error channels, while reconstructing a directed coupling map to restore connectivity constraints during transpilation. We compare four twin variants (CSV-built, backend-derived simulator, backend-derived noise model, and fake-backend snapshots) under a common execution and validation protocol. Experiments on two IBM QPUs, ibm_brisbane and ibm_sherbrooke, use randomized five-qubit circuits of depths 10, 20, and 30 across four optimization levels. Weighted Jaccard similarity indicates that twins constructed from downloadable calibration CSV data often achieved the closest agreement with hardware, while backend-derived twins provided competitive and practical baselines. The results further show that agreement depends on both the target device and the transpilation settings, underscoring the need to validate digital twins for the specific execution setup rather than assuming transferability across devices.
Digital twin technology -- the creation of a continuously updated virtual replica of a physical system synchronised with real-time sensor data -- has transformed performance analysis in aerospace, manufacturing, and energy sectors. Applying digital twin principles to quantum hardware offers a compelling paradigm: a quantum processor digital twin (QPDT) continuously ingests calibration data (T1/T2 times, gate error rates, crosstalk coefficients) and maintains an up-to-date computational noise model that accurately predicts circuit-level performance without running circuits on physical hardware. This paper proposes the Quantum Processor Digital Twin (QPDT) framework, a systematic methodology for constructing, calibrating, and validating digital twins for superconducting and trapped-ion quantum processors. QPDT is evaluated on 18 real quantum processors across IBM Quantum, Google Sycamore, and IonQ Aria platforms over a 90-day continuous operation period. Key results: QPDT achieves circuit fidelity prediction accuracy of 96.2% (mean absolute error 0.038 across 2,400 test circuits); twin synchronisation latency of 4.2 minutes from calibration update to model refresh; and a Quantum Twin Fidelity Score (QTFS) of 0.912. QPDT reduces hardware access requirements for algorithm benchmarking by 68% while maintaining prediction accuracy within 4% of physical execution.
Abstract We present an experimental implementation of the multiplayer Quantum Volunteer's Dilemma on noisy intermediate-scale quantum (NISQ) hardware, executed on the ibm_kingston backend via Qiskit Runtime. The game is evaluated for N = 2 to 9 players under four transpiler optimization levels, with 20 independent repetitions per configuration and 2048 shots per circuit, including post-processing readout error correction via mthree. Target-state fidelity decays with system size but remains above 70% (corrected) through N = 9. With readout correction, the global average payoff reproduces the quantum theoretical benchmark exactly for N ≤ 6 and exceeds the classical Nash equilibrium across the full tested range. Optimization level 2 is selected as the reference configuration after gate count analysis reveals that levels 2 and 3 produce identical transpiled circuits, with level 2 achieving superior fidelity stability. A Hamming distance analysis of raw measurement counts shows that single-qubit errors dominate at small N, with multi-qubit contributions growing beyond N = 6. A calibration-based digital twin captures global payoff trends but exhibits a linear fidelity decay profile that diverges from the hardware behavior at large N, exposing the limits of first-order independent per-qubit noise models. These results demonstrate that aggregate quantum advantage in multiplayer games is robust to NISQ noise conditions across the full tested range, while the practical observability of state-level advantage is constrained to N ≤ 8 under post-processed readout correction.
We present an experimental implementation of the multiplayer Quantum Volunteer's Dilemma on noisy intermediate-scale quantum (NISQ) hardware, executed on the ibm_kingston backend via Qiskit Runtime. The game is evaluated for N = 2 to 9 players under four transpiler optimization levels, with 20 independent repetitions per configuration and 2048 shots per circuit, including post-processing readout error correction via mthree. Target-state fidelity decays with system size but remains above 70% (corrected) through N = 9. With readout correction, the global average payoff reproduces the quantum theoretical benchmark exactly for N <= 6 and exceeds the classical Nash equilibrium across the full tested range. Optimization level 2 is selected as the reference configuration after gate count analysis reveals that levels 2 and 3 produce identical transpiled circuits, with level 2 achieving superior fidelity stability. A Hamming distance analysis of raw measurement counts shows that single-qubit errors dominate at small N, with multi-qubit contributions growing beyond N = 6. A calibration-based digital twin captures global payoff trends but exhibits a linear fidelity decay profile that diverges from the hardware behavior at large N, exposing the limits of first-order independent per-qubit noise models. These results demonstrate that aggregate quantum advantage in multiplayer games is robust to NISQ noise conditions across the full tested range, while the practical observability of state-level advantage is constrained to N <= 8 under post-processed readout correction.
We experimentally study error mitigation and finite-shot sampling on superconducting quantum hardware under a constrained execution budget. The study combines calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation on an IBM Quantum processor. Experiments are organized across ideal simulation, noise-model simulation, and physical-device execution to separate sampling uncertainty from device-induced error. We investigate how mitigation performance changes with circuit depth, effective noise scale, qubit connectivity, and measurement budget, and quantify accuracy using expectation-value error, mean-squared error, statistical uncertainty, and mitigation gain. A fixed hardware-execution budget is used to evaluate shot allocation strategies and repeated measurements without relying on unlimited sampling. The resulting analysis provides a hardware-aware characterization of when mitigation improves expectation-value estimation and when finite-shot fluctuations offset the benefit of additional mitigation overhead. The implementation uses contemporary Qiskit and IBM Quantum Runtime workflows and is designed to provide reproducible experimental evidence for error-mitigation studies on current quantum processors.
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Abstract Calibration summaries are used both to select physical qubits and to parameterize noisy emulators, creating a risk that agreement within a calibration-derived model is mistaken for validation on hardware. We test whether calibration-aware compiler rankings transfer to hardware using weighted-MaxCut instances implemented with the quantum approximate optimization algorithm. The evidence comprises four stages: 3240 historical calibration-derived simulations; a complete 54-pair hardware grid on three IBM Heron r2 processors; exact-circuit repeats 9.3–12.1 d later; and a contemporaneous five-arm refresh experiment. Full-calibration selection improves the median hardware approximation ratio by 0.74 percentage points (pp), with 29 resolved gains and 11 resolved losses. This is a mean-objective effect: its translation to exact-solution probability is instance- and size-dependent, and we do not extrapolate it beyond the tested n ⩽ 10 regime. A Qiskit Aer model constructed from the calibration state available before execution reproduced the direction of the measured full-calibration-versus-topology advantage in 35/54 comparisons, but systematically overestimated its size: the simulated advantage exceeded the subsequently measured hardware advantage by a median 1.35 pp. Regressing the measured hardware advantage on the simulated advantage gave a slope of 0.28 (workload-depth case-cluster 95% interval 0.06–0.52), rather than the unit slope of a calibrated predictor. The emulator identified the exact best of six backend-compiler configurations in only 5/18 cases (95% Wilson interval [0.125, 0.509]). By contrast, identical circuits preserved the compiler-effect sign in 16/18 later repeats ( r = 0.92 ). Refreshing the full-calibration mapping yielded a median +0.72 pp gain, whereas the calibration-score difference agreed in sign with the measured refresh benefit in only 9/18 cases. Calibration data are therefore useful for candidate discovery and timely refresh, but their scalar scores are not calibrated predictors of hardware performance or configuration ranking.