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arXiv:2505.11706 · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)

Forensics of Error Rates of Quantum Hardware

Rupshali Roy, Swaroop Ghosh

Published Nov 10, 2025• 1 citation
arXivHTMLPDF

Abstract

The qubit technologies, basis gate set, noise behavior, speed and coupling architecture are among the various factors that vary among various backends. Although third-party cloud providers offering quantum hardware as a service offer lower cost and flexibility to the users to choose from several qubit technologies, quantum hardware, and coupling maps; the actual execution of the program is not clearly visible to the customer. The success of the user program, in addition to various other metadata such as cost, performance, & number of iterations to converge, depends on the error rate of the backend used. Moreover, the third-party provider and/or tools (e.g., hardware allocator and mapper) may hold insider/outsider adversarial agents to conserve resources and maximize profit by running the quantum circuits on error-prone hardware. Thus it is important to gain visibility of the backend from various perspectives of the computing process e.g., execution, transpilation and outcomes. In this paper, we estimate the error rate of the backend from the original and transpiled circuit. Although many quantum services providers publish the error rates of their backends, we assume that such information may not be accurate and/or correspond to the actual hardware allocated to the program. For the forensics we propose two complementary approaches. First, we exploit the fact that qubit mapping and routing steps of the transpilation process select qubits and qubit pairs with low gate errors to minimize overall error accumulation. We leverage this to rank qubit links into bins and compare with publicly available data we are able to assign a bin rank within a difference of 2 with respect to the actual bin for upto$\mathbf{8 3. 5 \%}$of the qubit links in IBM Sherbrooke and$\mathbf{8 0 \%}$in IBM Brisbane, 127 qubit IBM backends. Second, we derive the error rates of the backends from a pool of programs by solving fidelity equations using numerical nonlinear optimizer. We achieve upto$92.7 \%(97.3 \%)$accuracy for single qubit (2 qubit) gate error rates.

DOI
10.1109/iccd65941.2025.00054

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The qubit technologies, basis gate set, noise behavior, speed and coupling architecture are among the various factors that vary among various backends. Although third-party cloud providers offering quantum hardware as a service offer lower cost and flexibility to the users to choose from several qubit technologies, quantum hardware, and coupling maps; the actual execution of the program is not clearly visible to the customer. The success of the user program, in addition to various other metadata such as cost, performance, & number of iterations to converge, depends on the error rate of the backend used. Moreover, the third-party provider and/or tools (e.g., hardware allocator and mapper) may hold insider/outsider adversarial agents to conserve resources and maximize profit by running the quantum circuits on error-prone hardware. Thus it is important to gain visibility of the backend from various perspectives of the computing process e.g., execution, transpilation and outcomes. In this paper, we estimate the error rate of the backend from the original and transpiled circuit. Although many quantum services providers publish the error rates of their backends, we assume that such information may not be accurate and/or correspond to the actual hardware allocated to the program. For the forensics we propose two complementary approaches. First, we exploit the fact that qubit mapping and routing steps of the transpilation process select qubits and qubit pairs with low gate errors to minimize overall error accumulation. We leverage this to rank qubit links into bins and compare with publicly available data we are able to assign a bin rank within a difference of 2 with respect to the actual bin for upto83.5%\mathbf{8 3. 5 \%}83.5%of the qubit links in IBM Sherbrooke and80%\mathbf{8 0 \%}80%in IBM Brisbane, 127 qubit IBM backends. Second, we derive the error rates of the backends from a pool of programs by solving fidelity equations using numerical nonlinear optimizer. We achieve upto92.7%(97.3%)92.7 \%(97.3 \%)92.7%(97.3%)accuracy for single qubit (2 qubit) gate error rates.
Many third-party cloud providers set up quantum hardware as a service that includes a wide range of qubit technologies and architectures to maximize performance at minimal cost. However, there is little visibility to where the execution of the circuit is taking place. This situation is similar to the classical cloud. The difference in the quantum scenario is that the success of the user program is highly reliant on the backend used. Besides, the third-party provider may be untrustworthy and execute the quantum circuits on less efficient and more error-prone hardware to maximize profit. Thus, gaining visibility on the backend from various aspects will be valuable. Effective forensics can have many applications including establishing trust in quantum cloud services. We introduce the problem of forensics in the domain of quantum computing. We trace the coupling map of the hardware where the transpilation of the circuit took place from the transpiled program. We perform experiments on various coupling topologies (linear, T-shaped, H-shaped, and loop) on IBM backends. We can derive the coupling map from the transpiled circuits with complete accuracy for almost every transpiled circuit we considered. We could correctly trace 97.33% of the programs to the correct backend.
Third-party cloud providers offer quantum hardware as a service enabling flexibility to the customers to opt from varied quantum hardware, qubit technologies and topologies. However, the actual execution of the program on the desired target hardware remains opaque to the user. On one hand, the program performance, along with various other metadata such as cost, performance, & number of iterations to converge, is dependent on the quality of the backend chosen. on the other hand, the third-party provider and/or tools (e.g., hardware schedulers) may maximize profit by running the quantum circuits on poor quality backend while charging for the high quality backend. Existing approaches to mitigate this opaqueness rely on forensics of error rates and coupling topology from transpiled circuit. We note that program queue depth and execution time are well correlated with the backend and therefore, can reveal vital information about the hardware and aid in forensic analysis to address the opaqueness.
There is a steady growth in research and demand for real quan- tum hardware in the Noisy Intermediate-Scale Quantum (NISQ) era of quantum computing. This prompts many third-party cloud providers to set up quantum hardware as a service that includes a wide range of qubit technologies and architectures to maximize performance at minimal cost. Quantum circuits submitted to these services are the fruits of the efforts invested by the designers. But these third-party cloud compilers (who offer more efficient alter- natives to established compilers) can make user circuits/programs vulnerable to various security breaches. Communication channels for transmitting quantum information also need to be developed such that there is end to end encryption. There is little to no visibil- ity on where the execution of the circuit is actually taking place. The success of the user program is highly reliant on the backend that was used for execution. Besides, the third-party provider and/or tools (e.g., hardware mapper and allocator) may be untrustworthy and execute the quantum circuits on less efficient and more error- prone hardware to conserve resources and maximize profit. These vulnerabilities in the quantum system could leak confidential data, cause loss of intellectual property rights of designers, cause loss of access control, corrupt user programs et cetera. Thus, it is imper- ative to identify these security vulnerabilities and create defense strategies to protect quantum programs, thus helping to maintain the integrity of quantum information across the software stack. My thesis aims to help address these vulnerabilities and opacities and address them.
We evaluate calibration-based digital twins for IBM Quantum hardware, aiming to reproduce hardware measurement outcomes on classical simulators. We present a workflow that builds twins from downloadable calibration CSV files by mapping coherence times, gate and readout error rates, and operation durations to thermal-relaxation, depolarizing, and readout error channels, while reconstructing a directed coupling map to restore connectivity constraints during transpilation. We compare four twin variants (CSV-built, backend-derived simulator, backend-derived noise model, and fake-backend snapshots) under a common execution and validation protocol. Experiments on two IBM QPUs, ibm_brisbane and ibm_sherbrooke, use randomized five-qubit circuits of depths 10, 20, and 30 across four optimization levels. Weighted Jaccard similarity indicates that twins constructed from downloadable calibration CSV data often achieved the closest agreement with hardware, while backend-derived twins provided competitive and practical baselines. The results further show that agreement depends on both the target device and the transpilation settings, underscoring the need to validate digital twins for the specific execution setup rather than assuming transferability across devices.
Reliably executing quantum algorithms on noisy intermediate-scale quantum (NISQ) devices is challenging, as they are severely constrained and prone to errors. Efficient quantum circuit compilation techniques are therefore crucial for overcoming their limitations and dealing with their high error rates. These techniques consider the quantum hardware restrictions, such as the limited qubit connectivity, and perform some transformations to the original circuit that can be executed on a given quantum processor. Certain compilation methods use error information based on calibration data to further improve the success probability or the fidelity of the circuit to be run. However, it is uncertain to what extent incorporating calibration information in the compilation process can enhance the circuit performance. For instance, considering the most recent error data provided by vendors after calibrating the processor might not be functional enough as quantum systems are subject to drift, making the latest calibration data obsolete within minutes. In this paper, we explore how different usage of calibration data impacts the circuit fidelity, by using several compilation techniques and quantum processors (IBM Perth and Brisbane). To this aim, we implemented a framework that incorporates some of the state-of-the-art noise-aware and non-noise-aware compilation techniques and allows the user to perform fair comparisons under similar processor conditions. Our experiments yield valuable insights into the effects of noise-aware methodologies and the employment of calibration data. The main finding is that pre-processing historical calibration data can improve fidelity when real-time calibration data is not available due to factors such as cloud service latency and waiting queues between compilation and execution on the quantum backend.
Cloud-based quantum service providers allow multiple users to run programs on shared hardware concurrently to maximize resource utilization and minimize operational costs. This multi-tenant computing (MTC) model relies on the error parameters of the hardware for fair qubit allocation and scheduling, as error-prone qubits can degrade computational accuracy asymmetrically for users sharing the hardware. To maintain low error rates, quantum providers perform periodic hardware calibration, often relying on third-party calibration services. If an adversary within this calibration service misreports error rates, the allocator can be misled into making suboptimal decisions even when the physical hardware remains unchanged. We demonstrate such an attack model in which an adversary strategically misreports qubit error rates to reduce hardware throughput, and probability of successful trial (PST) for two previously proposed allocation frameworks, i.e. Greedy and Community-Based Dynamic Allocation Partitioning (COMDAP). Experimental results show that adversarial misreporting increases execution latency by 24% and reduces PST by 7.8%. We also propose to identify inconsistencies in reported error rates by analyzing statistical deviations in error rates across calibration cycles.