Abstract A topology-driven suitability estimator answers whether a Max-Cut instance deserves quantum hardware. This paper asks the question that estimator cannot: does the answer change with the device? Extending the QSE framework from noiseless simulation to calibration-conditioned noise models of three IBM chip generations — Falcon (Guadalupe, cx), Eagle (Brisbane, ecr), and Heron (Torino, cz) — we evaluate depth-1 QAOA on 100 graphs from 12 structural families at N=10 and N=12, producing 300 physically valid (graph, device) evaluations. Three findings emerge. First, a negative baseline stronger than any in the noiseless literature: under calibrated noise, p=1 QAOA loses to a 15- ordering-averaged greedy heuristic on 300 of 300 instances (mean ratios 0.759 vs. 0.934), and even noiseless p=1 QAOA loses on all instances (0.803). Second, the degree of loss is predictable and device-dependent: a random forest reaches graph-grouped CV R2 = 0.431±0.086 from topology alone and 0.467±0.085 when calibration and transpilation features are added; a median-split relativeamenability classifier attains accuracy 0.77 and ROC-AUC 0.858 from topology alone, with average clustering the dominant signal (r = 0.56 with quantum utility). Third, a diagnostic negative result: a classifier asked to pick the better of the two modern backends per graph fails completely (AUC 0.434 vs. base rate 0.57) — and the failure is correct, because per-graph Torino–Brisbane differences sit at the shot-noise floor (paired t-test p = 0.03–0.07 across simulator seeds), whereas the Falcon–Eagle generation gap is decisive (p ≈ 10−28). A 4096-shot rerun confirms the diagnosis in both directions: the tie resolves (p = 2.5×10−11, Torino ahead by 0.004 in mean ratio) and the classifier rises to AUC 0.64 — a real but operationally minor ranking. Device-conditioning matters at the granularity of chip generations, not of individual healthy devices. An extension to the original 137-graph QSE benchmark at N=16 (411 further evaluations) confirms every finding and strengthens all learnability results (ratio R2 = 0.82; 1 amenability AUC 0.966; 0 QAOA wins in 711 total evaluations), and the full benchmark executed on three Heron R2 production devices (300 hardware evaluations, 94 s of QPU time) validates the study end-to-end: snapshot predictions hold at MAE ≤ 0.010, QAOA wins 0 of 1,221 evaluations overall, the amenability classifier transfers to hardware labels (AUC 0.827; 94% label agreement), and same-generation devices separate at 1024 shots (p ≤ 2.6 × 10−3) by an operationally minor 0.010. We also document how the greedy-gap hardness signal central to QSE collapses below N=16 (same-protocol RF R2 falls from 0.306 to 0.076; transitivity correlation from −0.564 to −0.351) — re-derivation on the original benchmark exposing a greedy-protocol difference that confounds naive cross-study comparisons — and two engineering failures — a ZZ-phase sign-convention bug caught by a cross-simulator parity check, and transpiler gatedirection faults in legacy Falcon noise models — whose diagnoses shaped the final pipeline.
Abstract A topology-driven suitability estimator answers whether a Max-Cut instance deserves quantum hardware. This paper asks the question that estimator cannot: does the answer change with the device? Extending the QSE framework from noiseless simulation to calibration-conditioned noise models of three IBM chip generations — Falcon (Guadalupe, cx), Eagle (Brisbane, ecr), and Heron (Torino, cz) — we evaluate depth-1 QAOA on 100 graphs from 12 structural families at N=10 and N=12, producing 300 physically valid (graph, device) evaluations. Three findings emerge. First, a negative baseline stronger than any in the noiseless literature: under calibrated noise, p=1 QAOA loses to a 15- ordering-averaged greedy heuristic on 300 of 300 instances (mean ratios 0.759 vs. 0.934), and even noiseless p=1 QAOA loses on all instances (0.803). Second, the degree of loss is predictable and device-dependent: a random forest reaches graph-grouped CV R2 = 0.431±0.086 from topology alone and 0.467±0.085 when calibration and transpilation features are added; a median-split relativeamenability classifier attains accuracy 0.77 and ROC-AUC 0.858 from topology alone, with average clustering the dominant signal (r = 0.56 with quantum utility). Third, a diagnostic negative result: a classifier asked to pick the better of the two modern backends per graph fails completely (AUC 0.434 vs. base rate 0.57) — and the failure is correct, because per-graph Torino–Brisbane differences sit at the shot-noise floor (paired t-test p = 0.03–0.07 across simulator seeds), whereas the Falcon–Eagle generation gap is decisive (p ≈ 10−28). A 4096-shot rerun confirms the diagnosis in both directions: the tie resolves (p = 2.5×10−11, Torino ahead by 0.004 in mean ratio) and the classifier rises to AUC 0.64 — a real but operationally minor ranking. Device-conditioning matters at the granularity of chip generations, not of individual healthy devices. An extension to the original 137-graph QSE benchmark at N=16 (411 further evaluations) confirms every finding and strengthens all learnability results (ratio R2 = 0.82; 1 amenability AUC 0.966; 0 QAOA wins in 711 total evaluations), and the full benchmark executed on three Heron R2 production devices (300 hardware evaluations, 94 s of QPU time) validates the study end-to-end: snapshot predictions hold at MAE ≤ 0.010, QAOA wins 0 of 1,221 evaluations overall, the amenability classifier transfers to hardware labels (AUC 0.827; 94% label agreement), and same-generation devices separate at 1024 shots (p ≤ 2.6 × 10−3) by an operationally minor 0.010. We also document how the greedy-gap hardness signal central to QSE collapses below N=16 (same-protocol RF R2 falls from 0.306 to 0.076; transitivity correlation from −0.564 to −0.351) — re-derivation on the original benchmark exposing a greedy-protocol difference that confounds naive cross-study comparisons — and two engineering failures — a ZZ-phase sign-convention bug caught by a cross-simulator parity check, and transpiler gatedirection faults in legacy Falcon noise models — whose diagnoses shaped the final pipeline.
Abstract Quantum processing units are scarce. Schedulers dispatch Max-Cut subgraphs to them anyway, rarely pausing to ask whether a cheap classical heuristic would have closed the gap just as well. This routing blindness wastes exactly the resource it can least afford to waste. QSE—a Topology-Driven Quantum Suit-ability Estimator—answers a narrower question than either QAOA or a classical heuristic can answer alone. Using only polynomial-time graph topology features, its four-phase pipeline routes each Max-Cut subgraph to the Quantum Approximate Optimization Algorithm (QAOA), to a classical greedy heuristic, or to human review, whichever the topology signal warrants. Central to this decision is a single quantity: the expected greedy gap, f cmax = 1 − ¯ c greedy /c *. It captures how far a 15-ordering-averaged greedy heuristic falls short of the exact Max-Cut optimum—no more, no less. 137 graphs, drawn from 18 structural families at N = 16, clear three pre-registered validation bars. Hardness exists (max(f cmax) = 0.2444); a cross-validated random forest learns it from topology alone (R 2 RF = 0.527 ± 0.11); and, more tellingly, a single feature—transitivity—tracks it almost linearly (|r| = 0.676). Reaching these results required repairing a self-calibrating sign-alignment layer for QAOA simulation, introduced after two earlier implementations silently violated the [0, m] physicality bound on every one of 105 runs; the repair eliminates the violation entirely. Trained on the resulting 105 physically valid QAOA evaluations , a meta-router (regressor R 2 CV = 0.506 ± 0.119; classifier accuracy 76.2%, ROC-AUC 0.834) feeds a production scheduler. That scheduler computes a polynomial-time spectral proxy for hardness and reports per-decision uncertainty as a tree-ensemble spread. Rather than forcing a verdict, ambiguous cases are downgraded to REVIEW. Alongside these results, we document three classes of engineering failure—a Hamiltonian sign-convention bug, a graph-reconstruction seed mismatch, and five fabricated-input bugs in an earlier scheduler—each diagnosed and corrected, since the diagnoses prove as informative as the final numbers.
Abstract Calibration summaries are used both to select physical qubits and to parameterize noisy emulators, creating a risk that agreement within a calibration-derived model is mistaken for validation on hardware. We test whether calibration-aware compiler rankings transfer to hardware using weighted-MaxCut instances implemented with the quantum approximate optimization algorithm. The evidence comprises four stages: 3240 historical calibration-derived simulations; a complete 54-pair hardware grid on three IBM Heron r2 processors; exact-circuit repeats 9.3–12.1 d later; and a contemporaneous five-arm refresh experiment. Full-calibration selection improves the median hardware approximation ratio by 0.74 percentage points (pp), with 29 resolved gains and 11 resolved losses. This is a mean-objective effect: its translation to exact-solution probability is instance- and size-dependent, and we do not extrapolate it beyond the tested n ⩽ 10 regime. A Qiskit Aer model constructed from the calibration state available before execution reproduced the direction of the measured full-calibration-versus-topology advantage in 35/54 comparisons, but systematically overestimated its size: the simulated advantage exceeded the subsequently measured hardware advantage by a median 1.35 pp. Regressing the measured hardware advantage on the simulated advantage gave a slope of 0.28 (workload-depth case-cluster 95% interval 0.06–0.52), rather than the unit slope of a calibrated predictor. The emulator identified the exact best of six backend-compiler configurations in only 5/18 cases (95% Wilson interval [0.125, 0.509]). By contrast, identical circuits preserved the compiler-effect sign in 16/18 later repeats ( r = 0.92 ). Refreshing the full-calibration mapping yielded a median +0.72 pp gain, whereas the calibration-score difference agreed in sign with the measured refresh benefit in only 9/18 cases. Calibration data are therefore useful for candidate discovery and timely refresh, but their scalar scores are not calibrated predictors of hardware performance or configuration ranking.
Full-pipeline benchmark of the Quantum Approximate Optimization Algorithm (QAOA) against classical combinatorial solvers on a weighted Max-Cut formulation of exam-scheduling conflict minimization. Compares random assignment, greedy heuristic, 2-opt local search, exact ILP (OR-Tools), and QAOA — first via noisy local simulation on an 18-qubit validation subset, then via live execution on IBM's ibm_marrakesh (Heron r2) processor at the full 42-qubit scale. Uses shot-weighted expected-value scoring throughout rather than best-observed-sample reporting. At 18 qubits QAOA reaches 95.4% of the proven optimum; at 42 qubits the hardware run's expected value falls below random guessing (49.05% vs 50.00%), with all 4,096 shots returning distinct bitstrings — the signature of decoherence overwhelming the circuit. Includes causal analysis of the failure mode and outlines planned comparison against quantum annealing hardware.
Qubit layout selection determining which physical qubits a logical circuit occupies on a superconducting processor is fundamentally a noise-field sampling problem. On IBM Heron r1 and Heron r2 devices, two-qubit gate error varies by nearly one order of magnitude (7– $9\times $ ) across qubit pairs on the same chip, causing measured fidelity differences up to 0.903 from layout choice alone. We introduce the Gate Noise Sensitivity Index (GNSI), a calibration-weighted linear combination of per-qubit readout error and per-edge two-qubit gate error, derived analytically as a first-order approximation of circuit fidelity under independent, heterogeneous noise channels. For 12 backend–circuit combinations on three IBM processors (133-qubit Heron r1 and 156-qubit Heron r2), GNSI scores are computed for the full pool of 1,320 computationally enumerated candidate layouts; the top-ranked (GNSI-BEST) and bottom-ranked (GNSI-WORST) layouts are then executed on hardware. GNSI-BEST ranks first by score in all 12 instances (Hit@1 = 100% within the enumerated candidate pool) and consistently achieves higher measured fidelity than GNSI-WORST, with Spearman rank correlation ρ=0.926±0.016 and statistically significant fidelity separation in 9 of 12 paired tests. Initial hardware comparisons on ibm_fez ( n=5 ) show GNSI-BEST matching or exceeding SABRE-selected fidelity. We further identify a depth-dependent regime transition: gate-error heterogeneity appears to govern ranking in shallow circuits (depth ≤15 ), while qubit-specific T1 variation may dominate for deeper circuits (depth ≥20 ). The analytic regime boundary d∗(b) , computable from calibration data alone, shows agreement within ±2 depth layers across all three backends in initial comparisons; GNSI-Extended incorporating the decoherence term receives an initial hardware comparison on two circuits, with full validation left to future work. These results suggest that layout-dependent fidelity variation may be governed by a calibration-predictable noise field, with direct implications for compiler design and noise-adaptive quantum circuit execution.
This study presents a rigorous empirical evaluation of the Quantum Approximate Optimization Algorithm (QAOA) within a hybrid quantum-classical framework for solving the NP-hard Max-Cut problem. Using Python and Qiskit Aer statevector simulations, we benchmark QAOA (depths p = 2 and p = 3) against established classical algorithms, including simulated annealing, the Goemans–Williamson algorithm, and greedy heuristics, across Erdős–Rényi and regular graphs with 4 to 20 nodes (100 instances per size). Results demonstrate that low-depth QAOA suffers from significant performance degradation, achieving a 0.467 approximation ratio at 20 nodes compared to 0.856 for Goemans–Williamson, alongside a 210× runtime overhead. Convergence analysis further reveals low optimality probabilities and high iteration costs, highlighting limitations of variational optimization in NISQ-era devices. This work provides a reproducible benchmarking framework and contributes to a realistic assessment of near-term quantum advantage.
This paper presents a reproducible, audit-ready quantum hardware experiment for minimal cut set (MCS) inference on reactor fault tree subtrees using IBM Quantum hardware. Eight two-qubit subtrees were selected from a Phase 2B reactor-scale fault tree corpus spanning four nuclear hazard families (EQK, LOCA, TRANS, SGTR). Classical baselines were computed with SCRAM 0.16.2, yielding two order-1 MCS per instance. Shallow p = 1 Quantum Alternating Operator Ansatz (QAOA+) circuits were constructed using the Constraint-Level QUBO (CL-QUBO) encoding from Peters (2026b), transpiled to ibm_torino, and executed as batch jobs totaling 57,344 shots across four experiments. Raw hardware results showed apparent infeasible leakage of 13.2% on the hw = 0 state. A dedicated four-circuit readout calibration protocol revealed that this leakage was almost entirely attributable to readout error: after confusion-matrix correction (κ = 1.56), the baseline experiment concentrates 98.3% of probability mass on the MCS manifold (hw = 1), with residual infeasible mass of 0.5%. Extension experiments substantially broaden the empirical foundation. Cross-pair validation on three additional qubit pairs (ibm_torino pairs 61–62 and 36–48; ibm_marrakesh pair 6–7) confirms that corrected MCS fidelity exceeds 95% across all tested physical qubit assignments (range 95.2%–98.3%), with the best pairs achieving 98.2% (ibm_marrakesh 6–7) and 97.9% (ibm_torino 61–62). A QAOA depth sweep (p ∈ {1, 2, 3}) on ibm_torino pair 0–1 quantifies noise–depth tradeoffs: because the mixer is inactive (β = 0), the observed redistribution from hw = 2 toward hw = 1 (7.8% at p = 1, 25.6% at p = 2, 40.9% at p = 3) is attributable to gate noise rather than productive mixing, with infeasible hw = 0 mass rising concurrently from 0.2% to 7.2%. A three-qubit exactly-one constraint experiment on ibm_torino triple 0–1–2 achieves 92.2% corrected hw = 1 mass from a feasible initialization, demonstrating that the CL-QUBO framework extends beyond two-qubit OR gates to richer constraint types on quantum hardware. Hard-start initialization experiments confirm that p = 1 circuits do not induce sufficient mixing to recover MCS states from non-minimal initializations, with this conclusion stable across independent replication and all tested qubit pairs. Complete experimental artifacts with SHA-256 verification are provided under the DOI above.