This study primarily investigates variations in the radio-frequency (RF) performance characteristics of components within flip-chip packaged superconducting qubit chips. By comparing changes in the lumped-element parameters of identical qubit chip physical structures across different packaging architectures, we analyze the evolving trends in the qubits' energy dissipation models and nonlinear parameters. Simulation and numerical computation results reveal that the metal layers proximal to the chip surface and the microbumps within the flip-chip architecture significantly impact structural parameters such as the resonant frequency and self-capacitance of resonant elements (including the qubits and readout cavities). This influence manifests as an increase in self-capacitance, consequently leading to an overall decrease in resonant frequency. Furthermore, structures such as the XY/Z control lines and the qubit-readout cavity coupling elements exhibit coupling strength of different change trends due to the altered electromagnetic field distribution within the packaging structure. Additionally, the direction of electromagnetic field leakage during coupling undergoes a change.
This study primarily investigates variations in the radio-frequency (RF) performance characteristics of components within flip-chip packaged superconducting qubit chips. By comparing changes in the lumped-element parameters of identical qubit chip physical structures across different packaging architectures, we analyze the evolving trends in the qubits' energy dissipation models and nonlinear parameters. Simulation and numerical computation results reveal that the metal layers proximal to the chip surface and the microbumps within the flip-chip architecture significantly impact structural parameters such as the resonant frequency and self-capacitance of resonant elements (including the qubits and readout cavities). This influence manifests as an increase in self-capacitance, consequently leading to an overall decrease in resonant frequency. Furthermore, structures such as the XY/Z control lines and the qubit-readout cavity coupling elements exhibit coupling strength of different change trends due to the altered electromagnetic field distribution within the packaging structure. Additionally, the direction of electromagnetic field leakage during coupling undergoes a change.
In superconducting quantum processors, the predictability of device parameters is of increasing importance as many labs scale up their systems to larger sizes in a 3D-integrated architecture. In particular, the properties of superconducting resonators must be controlled well to ensure high-fidelity multiplexed readout of qubits. Here we present a method, based on conformal mapping techniques, to predict a resonator's parameters directly from its 2D cross-section, without computationally heavy and time-consuming 3D simulation. We demonstrate the method's validity by comparing the calculated resonator frequency and coupling quality factor with those obtained through 3D finite-element-method simulation and by measurement of 15 resonators in a flip-chip-integrated architecture. We achieve a discrepancy of less than 2% between designed and measured frequencies, for 6-GHz resonators. We also propose a design method that reduces the sensitivity of the resonant frequency to variations in the inter-chip spacing.
Abstract As quantum computing evolves from the multi‐qubit stage to large multimodularprocessors, addressability and scalability of quantum hardware will require 3D integration and packaging. The advancement of flip‐chip technology is critical to enabling progress in this area. However, various types of coupling, such as capacitive, inductive, and galvanic, still require systematic research into the principles, quantification, and loss mechanisms. In this article, different types of 3D architecture are examined using flip‐chip technology. The and superconducting resonators with qubit circuits are designed in a modular configuration consisting of two silicon substrates. This arrangement allows numerical analysis and systematic experimental investigation of capacitive, inductive, and galvanic coupling mechanisms. The transmission of short control pulses for fast qubit manipulation is demonstrated and the feasibility of quantum state transfer is theoretically explored, highlighting the potential of this approach for scalable quantum processors. Particular focus is also on the fabrication technology of superconducting indium bumps between silicon substrates.
Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure high performance already at the scale of dozens of qubits. Signal crosstalk causes inadvertent driving of quantum gates, which will adversely affect quantum gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting quantum processors with signal-crosstalk performance competitive with those reported in other platforms. For capacitively coupled qubit-drive lines, we find on-resonant crosstalk better than − 27 dB (average − 37 dB). For inductively coupled magnetic-flux-drive lines, we find less than 0.13% direct-current flux crosstalk (average 0.05%). These observed crosstalk levels are adequately small and indicate a decreasing trend with increasing distance, which is promising for further scaling up to larger numbers of qubits. We discuss the implications of our results for the design of a low-crosstalk on-chip signal-delivery architecture, including the influence of a shielding tunnel structure, potential sources of crosstalk, and estimation of crosstalk-induced qubit-gate error in scaled-up quantum processors. Published by the American Physical Society 2024
Quantum computing is advancing rapidly, with superconducting quantum computing (SQC) emerging as one of the most promising platforms for scalable quantum information processing. In contrast to fabrication-focused approaches prevalent in current literature, this work presents a fully simulation-based design and tuning methodology for a small-scale superconducting quantum chip - addressing practical limitations posed by fabrication resource constraints - and consequently excludes physical chip fabrication or real-time performance evaluation (e.g., fidelity and error rate measurements). A meticulous, step-by-step electromagnetic simulation was conducted on the chip, designed using Qiskit Metal and Ansys Electronics, with qubit parameters tuned and verified using the Lumped Oscillator Model (LOM) and Energy Participation Ratio (EPR) methods. The design achieves good parameter convergence with relative tuning error rates (Δ%) below 0.05% after 15 adaptive passes and approximately 50,000 solved mesh elements, yielding an Energy Participation Ratio (EPR) of 91.8 % for the chip substrate (Silicon). Furthermore, the study includes a theoretical comparison between two fundamental qubit-qubit coupling schemes. A key contribution of this work lies in systematically analyzing how geometric variations in qubit design affect critical quantum parameters such as qubit frequencies, anharmonicities, coupling strengths, and dispersive shifts - thereby offering a comprehen-sive, simulation-driven framework for early-stage quantum chip prototyping.
Abstract As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence ( T 1 , T 2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.
In the design of superconducting quantum chips, the control and readout of the quantum bit (qubit) are realized through interactions with other components in the circuit, such as drive lines, flux lines and readout resonator. Depending on the design, these interactions employ either an inductive or capacitive coupling scheme. Note that every interaction governs critical performance metrics for the chip, including gate fidelity, readout speed, and coherence times, a more effective and precise approach to extract the strength of the coupling is necessary. For most qubit designs, the structure of the qubit typically remains in the electrically small regime. Therefore, simulation software based on static fields and the Method of Moments (MoM), such as Q3D, is still applicable in most instances. However, as the number of qubits on a chip increases, Q3D faces challenges in effectively addressing the complex coupling and crosstalk issues present on the chip. In this work, we extend the lumped-element-based qubit model by using microwave network parameters and thus enable the simulation of the qubit for the Finite Element Method (FEM)-based 3D electromagnetic simulation software, such as HFSS. This approach is suitable for the determination of the capacitive coupling strength between the qubit and the drive line, as well as readout circuits. Furthermore, to address the inductive coupling between the qubit and the flux line, we propose a method in this work that directly computes the mutual inductance, which is implemented by determining the magnetic flux through the DC SQUID area, generated by the current port excitation in HFSS. The proposed methodologies not only effectively extracts the key qubit design parameters, but also offer broader applicability for analysing complex crosstalk in multi-qubit chip designs.