Sandoko Kosen, Hang-Xi Li, Marcus Rommel, Robert Rehammar, M. Caputo, Leif Grönberg, Jorge Fernández-Pendás, Anton Frisk Kockum, Janka Biznárová, Liangyu Chen, Christian Križan, Andreas Nylander, Amr Osman, Anita Fadavi Roudsari, Daryoush Shiri, Giovanna Tancredi, Joonas Govenius, Jonas Bylander
Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure high performance already at the scale of dozens of qubits. Signal crosstalk causes inadvertent driving of quantum gates, which will adversely affect quantum gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting quantum processors with signal-crosstalk performance competitive with those reported in other platforms. For capacitively coupled qubit-drive lines, we find on-resonant crosstalk better than − 27 dB (average − 37 dB). For inductively coupled magnetic-flux-drive lines, we find less than 0.13% direct-current flux crosstalk (average 0.05%). These observed crosstalk levels are adequately small and indicate a decreasing trend with increasing distance, which is promising for further scaling up to larger numbers of qubits. We discuss the implications of our results for the design of a low-crosstalk on-chip signal-delivery architecture, including the influence of a shielding tunnel structure, potential sources of crosstalk, and estimation of crosstalk-induced qubit-gate error in scaled-up quantum processors. Published by the American Physical Society 2024
Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure high performance already at the scale of dozens of qubits. Signal crosstalk causes inadvertent driving of quantum gates, which will adversely affect quantum gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting quantum processors with signal-crosstalk performance competitive with those reported in other platforms. For capacitively coupled qubit-drive lines, we find on-resonant crosstalk better than − 27 dB (average − 37 dB). For inductively coupled magnetic-flux-drive lines, we find less than 0.13% direct-current flux crosstalk (average 0.05%). These observed crosstalk levels are adequately small and indicate a decreasing trend with increasing distance, which is promising for further scaling up to larger numbers of qubits. We discuss the implications of our results for the design of a low-crosstalk on-chip signal-delivery architecture, including the influence of a shielding tunnel structure, potential sources of crosstalk, and estimation of crosstalk-induced qubit-gate error in scaled-up quantum processors. Published by the American Physical Society 2024
Maintaining or even improving gate performance with growing numbers of parallel controlled qubits is a vital requirement for fault-tolerant quantum computing.For superconducting quantum processors, though isolated one-or two-qubit gates have been demonstrated with high fidelity, implementing these gates in parallel commonly shows worse performance.Generally, this degradation is attributed to various crosstalks between qubits, such as quantum crosstalk due to residual inter-qubit coupling.An understanding of the exact nature of these crosstalks is critical to figuring out respective mitigation schemes and improved qubit architecture designs with low crosstalk.Here we give a theoretical analysis of quantum crosstalk impact on simultaneous gate operations in a qubit architecture, where fixed-frequency transmon qubits are coupled via a tunable bus, and sub-100-ns controlled-Z (CZ) gates can be realized by applying a baseband flux pulse on the bus.Our analysis shows that for microwave-driven single-qubit gates, the dressing from the qubit-qubit coupling can cause non-negligible cross-driving errors when qubits operate near frequency collision regions.During CZ gate operations, although unwanted nearest-neighbor interactions are nominally turned off, sub-MHz parasitic next-nearest-neighbor interactions involving spectator qubits can still exist, causing considerable leakage or control error when one operates qubit systems around these parasitic resonance points.To ensure high-fidelity simultaneous operations, a request could be raised to figure out a better way to balance the gate error from target qubit systems themselves and the error from nonparticipating spectator qubits.Overall, our analysis suggests that towards useful quantum processors, the qubit architecture should be examined carefully in the context of high-fidelity simultaneous gate operations in a scalable qubit lattice.
We present a flip-chip architecture for an array of coupled superconducting qubits, in which circuit components reside inside individual microwave enclosures. In contrast to other flip-chip approaches, the qubit chips in our architecture are electrically floating, which guarantees a simple, fully modular assembly of capacitively coupled circuit components, such as qubit, control, and coupling structures as well as reduced crosstalk between the components. We validate the concept with a chain of three nearest neighbor coupled generalized flux qubits in which the center qubit acts as a frequency-tunable coupler. Using this coupler, we demonstrate a transverse coupling on/off ratio≈50, zz−crosstalk ≈0.7 kHz between resonant qubits and isolation between the qubit enclosures>60 dB.
Superconducting qubits have achieved exceptional gate fidelities, exceeding the error-correction threshold in recent years. One key ingredient of such improvement is the introduction of tunable couplers to control the qubit-to-qubit coupling through frequency tuning. Moving toward fault-tolerant quantum computation, increasing the number of physical qubits is another step toward effective error correction codes. Under a multiqubit architecture, flux control (Z) lines are crucial in tuning the frequency of the qubits and couplers. However, dense flux lines result in magnetic flux crosstalk, wherein magnetic flux applied to one element inadvertently affects neighboring qubits or couplers. This crosstalk obscures the idle frequency of the qubit when flux bias is applied, which degrades gate performance and calibration accuracy. In this study, we characterize flux crosstalk and suppress it in a multiqubit-coupler chip with multi-Z lines without adding additional readout for couplers. By quantifying the mutual flux-induced frequency shifts of qubits and couplers, we construct a cancellation matrix that enables precise compensation of non-local flux, demonstrating a substantial reduction in Z-line crosstalk from 56.5‰ to 0.13‰, which is close to statistical error. Flux compensation corrects the CZ SWAP measurement, leading to a symmetric map with respect to flux bias. Compared with a crosstalk-free calculated CZ SWAP map, the measured map indicates that our approach provides a near-zero crosstalk for the coupler-transmon system. These results highlight the effectiveness of our approach in enhancing flux crosstalk-free control and supporting its potential for scaling superconducting quantum processors.
The technological development of hardware heading toward universal fault-tolerant quantum computation requires a large-scale processing unit with high performance. While fluxonium qubits are promising with high coherence and large anharmonicity, their scalability has not been systematically explored. In this work, we propose a superconducting quantum information processor based on compact high-coherence fluxoniums with suppressed crosstalk, reduced design complexity, improved operational efficiency, high-fidelity gates, and resistance to parameter fluctuations. In this architecture, the qubits are readout dispersively using individual resonators connected to a common bus and manipulated via combined on-chip RF and DC control lines, both of which can be designed to have low crosstalk. A multi-path coupling approach enables exchange interactions between the high-coherence computational states and at the same time suppresses the spurious static ZZ rate, leading to fast and high-fidelity entangling gates. We numerically investigate the cross resonance controlled-NOT and the differential AC-Stark controlled-Z operations, revealing low gate error for qubit-qubit detuning bandwidth of up to 1 GHz. Our study on frequency crowding indicates high fabrication yield for quantum processors consisting of over thousands of qubits. In addition, we estimate low resource overhead to suppress logical error rate using the XZZX surface code. These results promise a scalable quantum architecture with high performance for the pursuit of universal quantum computation.
Single-qubit gates on superconducting quantum processors are typically implemented using microwave pulses applied through dedicated control lines. However, these microwave pulses may also drive other qubits due to crosstalk arising from capacitive coupling and wavefunction overlap in systems with closely spaced transition frequencies. Crosstalk and frequency crowding increase errors during simultaneous single-qubit operations relative to isolated gates, thus forming a major bottleneck for scaling superconducting quantum processors. In this work, we combine model-based qubit frequency optimization with pulse shaping to demonstrate crosstalk error mitigation in single-qubit gates on a 49-qubit superconducting quantum processor. We introduce and experimentally verify an analytical model of simultaneous single-qubit gate error caused by microwave crosstalk that depends on a given pulse shape. By employing a model-based optimization strategy of qubit frequencies, we minimize the crosstalk-induced error across the processor and achieve a mean simultaneous single-qubit gate fidelity of 99.96% for a 16-ns gate duration, approaching the mean individual gate fidelity. To further reduce the simultaneous error and required qubit frequency bandwidth on high-crosstalk qubit pairs, we introduce a crosstalk transition suppression (CTS) pulse shaping technique that minimizes the spectral energy around transitions inducing leakage and crosstalk errors. Finally, we combine CTS with model-based frequency optimization across the device and experimentally show a systematic reduction in the required qubit frequency bandwidth for high-fidelity simultaneous gates, supported by simulations of systems with up to 1000 qubits. By alleviating constraints on qubit frequency bandwidth for parallel single-qubit operations, this work represents an important step for scaling towards larger quantum processors.
This study primarily investigates variations in the radio-frequency (RF) performance characteristics of components within flip-chip packaged superconducting qubit chips. By comparing changes in the lumped-element parameters of identical qubit chip physical structures across different packaging architectures, we analyze the evolving trends in the qubits' energy dissipation models and nonlinear parameters. Simulation and numerical computation results reveal that the metal layers proximal to the chip surface and the microbumps within the flip-chip architecture significantly impact structural parameters such as the resonant frequency and self-capacitance of resonant elements (including the qubits and readout cavities). This influence manifests as an increase in self-capacitance, consequently leading to an overall decrease in resonant frequency. Furthermore, structures such as the XY/Z control lines and the qubit-readout cavity coupling elements exhibit coupling strength of different change trends due to the altered electromagnetic field distribution within the packaging structure. Additionally, the direction of electromagnetic field leakage during coupling undergoes a change.