This whitepaper identifies execution-time phase exposure as a missing diagnostic layer in quantum circuit evaluation. Quantum circuit performance is commonly evaluated through aggregate quantities such as gate count, circuit depth, total idle time, calibration data, error rates, and hardware coherence parameters such as T1 and T2. These quantities are necessary, but they do not identify when a qubit is actually carrying phase-sensitive quantum information whose preservation matters to the intended readout. The central observation is that idle time is not uniformly harmful. Idle time becomes consequential when it overlaps an active phase-bearing execution window: an interval in which phase-sensitive structure exists, persists, and remains relevant to a later readout. The whitepaper frames this distinction from a compact-fiber readout perspective and reports sanitized aggregate validation results from contemporary superconducting quantum hardware. The validation supports the claim that circuits with similar aggregate metrics can differ in observed performance because their idle intervals occur in different execution-time locations relative to phase-bearing structure. This record contains the whitepaper PDF only. It does not include circuit definitions, job identifiers, report schemas, implementation details, raw validation artifacts, or non-public workflow material.
This whitepaper identifies execution-time phase exposure as a missing diagnostic layer in quantum circuit evaluation. Quantum circuit performance is commonly evaluated through aggregate quantities such as gate count, circuit depth, total idle time, calibration data, error rates, and hardware coherence parameters such as T1 and T2. These quantities are necessary, but they do not identify when a qubit is actually carrying phase-sensitive quantum information whose preservation matters to the intended readout. The central observation is that idle time is not uniformly harmful. Idle time becomes consequential when it overlaps an active phase-bearing execution window: an interval in which phase-sensitive structure exists, persists, and remains relevant to a later readout. The whitepaper frames this distinction from a compact-fiber readout perspective and reports sanitized aggregate validation results from contemporary superconducting quantum hardware. The validation supports the claim that circuits with similar aggregate metrics can differ in observed performance because their idle intervals occur in different execution-time locations relative to phase-bearing structure. This record contains the whitepaper PDF only. It does not include circuit definitions, job identifiers, report schemas, implementation details, raw validation artifacts, or non-public workflow material.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
Superconducting qubit performance is commonly assessed using snapshot calibration metrics such as coherence time (T2) and readout error probability. While useful for short-term characterization, such static representations obscure temporal structure present in long-term device operation. This technical note presents a time-resolved empirical analysis of publicly available calibration data from the IBM Quantum Athens superconducting quantum processor. By treating calibration records as a chronologically ordered time series, the analysis reveals recurring temporal alignment between abrupt coherence collapses and short-lived bursts of elevated readout error. The analysis is descriptive and model-agnostic by design. No microscopic noise sources, control mechanisms, or causal relationships are inferred. The observations are restricted to pre–error-correction behavior and are intended to document non-stationary, structured behavior that is obscured when calibration data are interpreted solely as static snapshots. These observations are relevant for scheduling, benchmarking, and any methodology that assumes stationary calibration parameters.
Abstract Long-run quantum execution remains fundamentally constrained, not primarily by gate infidelity, but by cumulative instability of the rotating phase reference during runtime. While contemporary quantum control stacks rely on calibration, dynamical decoupling, and quantum error correction, these mechanisms operate reactively and assume that the underlying phase frame remains valid between interventions. This assumption breaks down as execution depth, runtime, and system size increase. This note reframes long-run execution failure as a phase-frame stability problem rather than a post-fault correction problem. Using empirical hardware-adjacent observations, it shows that longitudinal drift is structured, temporally correlated, and often collective across qubits, placing it outside the effective bandwidth of fast-noise suppression techniques. As a result, computation is frequently admitted under metastable conditions in which logical error amplification occurs despite unchanged physical gate metrics. Based on this empirical and structural analysis, the note identifies a missing architectural element: a preventive drift-bounding layer that constrains phase-frame deviation before execution proceeds. The argument is intentionally architectural rather than implementational. No hardware-specific parameters, algorithms, or corrective primitives are disclosed. The purpose of this document is to establish why scalable quantum execution requires preventive phase stabilization at the execution boundary, and why reactive correction alone cannot remove this limitation. Detailed theoretical foundations, validation pathways, and hardware-compatible realizations exist but are intentionally excluded from this public note.
Abstract Pulse-level calibration metrics — coherence times T₁ and T₂ measured through single-qubit Rabi and Ramsey sequences — are the standard by which quantum hardware providers certify device health. We demonstrate, through 191 circuit executions on three 156-qubit IBM Heron r2 processors (ibm_kingston, ibm_fez, and ibm_marrakesh), that these pulse-level metrics can give opposite conclusions to circuit-level diagnostics on the same device at the same time. Specifically, between experimental sessions on July 3 and July 5, 2026, IBM reported ibm_marrakesh T₂ improved from 303 µs to 340 µs (a 12% improvement), while the K–R scaling exponent α measured from GHZ circuit scaling increased from 1.406 to 3.811 (a 171% increase in coherent error dominance) and GHZ n = 2 infidelity rose from 0.018 to 0.204 — a 920% increase in circuit error. We further demonstrate that Ramsey circuit-context T₂ on qubit 0 is approximately 9–30 µs, compared to IBM-reported pulse-level T₂ of 32–340 µs — a discrepancy of 3–11×. We introduce five experimental demonstrations showing K–R circuit-level diagnostics detect degradation invisible to T₁/T₂, provide higher temporal sensitivity, enable algorithm failure prediction, and confirm the theoretical prediction αₜ v ₜᶜʰ + αₑₜₕₒ = 2 within 7% on real hardware. These findings establish circuit-level K–R diagnostics as a necessary complement to pulse-level calibration for operational quantum computing.
We present an analysis of quantum circuit fidelity across the full compilation stack, from high-level gate optimization through pulse-level control. We connect a C++ circuit optimizer to a per-gate Lindblad master-equation fidelity model whose decoherence channels are cross-validated against qiskit-dynamics and whose absolute predictions are benchmarked against execution on real hardware. Across a campaign of 4,452 experiment runs over 371 benchmark circuits, gate cancellation provides the dominant improvement (d=1.66, 72% of circuits improved), while circuit size and pulse duration are the strongest negative predictors of process fidelity (input gates r=−0.78; pulse duration r=−0.73, R2=0.53). A formal ablation study shows that pass ordering has no significant effect on two-qubit gate reduction (Kruskal--Wallis p=0.302). Comparing against Qiskit transpilation levels, we show that two-qubit gate count, not total gate count, is the hardware-relevant metric: our optimizer attains superior two-qubit reduction on structured circuits (87.8% on QFT, 100% on QAOA) whereas Qiskit's larger total-gate reduction is dominated by single-qubit (u3) consolidation. Finally, executing eight circuits on the IQM Resonance Garnet processor (8/8 jobs completed, job identifiers released) reveals that the model is a consistent upper bound: it preserves the relative difficulty ordering of circuits but overestimates absolute fidelity by a mean of 0.49, quantifying the error budget (crosstalk, leakage, readout) outside a T1/T2/depolarizing model. We release the framework, data, and scripts as open source.
Quantum processors have crossed the one-hundred-qubit mark, but noise continues to limit circuit performance, while full quantum error correction remains too costly for routine use. Error suppression and mitigation therefore play an important role in extracting value from current hardware, yet independent comparisons of commercial solutions on identical workloads and devices remain scarce. We benchmark IBM Qiskit Runtime, Q-CTRL Performance Management, and Qedma QESEM on IBM Pittsburgh, a 156-qubit IBM Quantum Heron r3 processor. For Sampler workloads, we run Bernstein-Vazirani, quantum phase estimation, GHZ-state preparation, and randomized mirror circuits with up to 100 measured qubits, comparing raw execution, IBM measurement twirling, and Q-CTRL. For Estimator workloads, we measure chain-averaged magnetization and correlation observables of an eight-layer transverse-field Ising circuit at 25, 50, and 75 qubits against an exact matrix-product-state reference, comparing IBM raw execution, IBM TREX plus twirling, Q-CTRL, and QESEM. Q-CTRL produced the best results on the three structured Sampler workloads while keeping reported QPU times within the same order as the IBM configurations. Across six Ising observable and system-size cases, aggregate mean absolute error was 0.0883 for IBM raw execution, 0.0807 for IBM TREX plus twirling, 0.0285 for Q-CTRL, and 0.0188 for QESEM. Relative to raw execution, Q-CTRL and QESEM reduced aggregate error by factors of 3.10 and 4.70, respectively, while QESEM used 7.5 to 11.1 times the reported QPU time of Q-CTRL. These results show that managed error suppression and mitigation can substantially improve current hardware performance, but with distinct accuracy and execution-time tradeoffs.