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Toward a Quantum Diagnostic Intelligence System: A Multi-Layer Architecture for Circuit-Level Assessment of Quantum Hardware Operational State

Ramakrishna Pasupuleti

Published Jul 22, 2026• 0 citations
Publisher

Abstract

Abstract We introduce Quantum Diagnostic Intelligence (QDI), a five-layer decision-support architecture for inferring the operational state of quantum processing units from circuit-level measurements. Pulse-level calibration metrics — coherence times T₁ and T₂ measured through single-qubit Rabi and Ramsey sequences — are the dominant industry standard for certifying quantum hardware health. We demonstrate, through 191 circuit executions on three 156-qubit IBM Heron r2 processors, that circuit-level measurements contain diagnostic information that T₁/T₂ may not capture. On ibm_marrakesh between July 3 and July 5, 2026, IBM-reported T₂ improved from 303 to 340 µs (+ 12%), while circuit-level GHZ scaling yielded α = 3.811, a QDI health score of 37.8/100 [95% CI: 7.6, 67.9], and a circuit infidelity increase of 920% at n = 2 qubits. The QDI architecture formalizes this observation through four operators: a diagnostic state classifier D(χ), a health score H(χ), a recommendation generator R(χ), and a drift forecast F(χ, t). Rules trained on ibm_kingston correctly classified ibm_fez and both ibm_marrakesh sessions without retuning (3/3 held-out tests; n = 4 total — feasibility demonstration only). We identify three scientific limitations of the current framework: operators rely on expert-designed rules rather than learned statistical models; ground truth (algorithm success/failure) has not yet been collected; and diagnostic state labels have not been validated by clustering analysis. Prospective validation on n ≥ 50 independent sessions is required before statistical claims about generalization can be made. The dataset, code, and QDI system are openly available.

DOI
10.21203/rs.3.rs-10394388/v1

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Abstract We introduce Quantum Diagnostic Intelligence (QDI), a five-layer decision-support architecture for inferring the operational state of quantum processing units from circuit-level measurements. Pulse-level calibration metrics — coherence times T₁ and T₂ measured through single-qubit Rabi and Ramsey sequences — are the dominant industry standard for certifying quantum hardware health. We demonstrate, through 191 circuit executions on three 156-qubit IBM Heron r2 processors, that circuit-level measurements contain diagnostic information that T₁/T₂ may not capture. On ibm_marrakesh between July 3 and July 5, 2026, IBM-reported T₂ improved from 303 to 340 µs (+ 12%), while circuit-level GHZ scaling yielded α = 3.811, a QDI health score of 37.8/100 [95% CI: 7.6, 67.9], and a circuit infidelity increase of 920% at n = 2 qubits. The QDI architecture formalizes this observation through four operators: a diagnostic state classifier D(χ), a health score H(χ), a recommendation generator R(χ), and a drift forecast F(χ, t). Rules trained on ibm_kingston correctly classified ibm_fez and both ibm_marrakesh sessions without retuning (3/3 held-out tests; n = 4 total — feasibility demonstration only). We identify three scientific limitations of the current framework: operators rely on expert-designed rules rather than learned statistical models; ground truth (algorithm success/failure) has not yet been collected; and diagnostic state labels have not been validated by clustering analysis. Prospective validation on n ≥ 50 independent sessions is required before statistical claims about generalization can be made. The dataset, code, and QDI system are openly available.
Pulse-level calibration metrics — coherence times T₁ and T₂ measured through single-qubit Rabi and Ramsey sequences — are the standard by which quantum hardware providers certify device health. We demonstrate, through 191 circuit executions on three 156-qubit IBM Heron r2 processors (ibm_kingston, ibm_fez, and ibm_marrakesh), that these pulse-level metrics can give opposite conclusions to circuit-level diagnostics on the same device at the same time. Specifically, between experimental sessions on July 3 and July 5, 2026, IBM reported ibm_marrakesh T₂ improved from 303 μs to 340 μs (a 12% improvement), while the K–R scaling exponent α measured from GHZ circuit scaling increased from 1.406 to 3.811 (a 171% increase in coherent error dominance) and GHZ n=2 infidelity rose from 0.018 to 0.204 — a 920% increase in circuit error. We further demonstrate that Ramsey circuit-context T₂ on qubit 0 is approximately 9–30 μs, compared to IBM-reported pulse-level T₂ of 32–340 μs — a discrepancy of 3–11×. We introduce five experimental demonstrations showing K–R circuit-level diagnostics detect degradation invisible to T₁/T₂, provide higher temporal sensitivity, enable algorithm failure prediction, and confirm the theoretical prediction αₜᵥₜᶜʰ + αₑₜₕₒ = 2 within 7% on real hardware. These findings establish circuit-level K–R diagnostics as a necessary complement to pulse-level calibration for operational quantum computing.
Abstract Pulse-level calibration metrics — coherence times T₁ and T₂ measured through single-qubit Rabi and Ramsey sequences — are the standard by which quantum hardware providers certify device health. We demonstrate, through 191 circuit executions on three 156-qubit IBM Heron r2 processors (ibm_kingston, ibm_fez, and ibm_marrakesh), that these pulse-level metrics can give opposite conclusions to circuit-level diagnostics on the same device at the same time. Specifically, between experimental sessions on July 3 and July 5, 2026, IBM reported ibm_marrakesh T₂ improved from 303 µs to 340 µs (a 12% improvement), while the K–R scaling exponent α measured from GHZ circuit scaling increased from 1.406 to 3.811 (a 171% increase in coherent error dominance) and GHZ n = 2 infidelity rose from 0.018 to 0.204 — a 920% increase in circuit error. We further demonstrate that Ramsey circuit-context T₂ on qubit 0 is approximately 9–30 µs, compared to IBM-reported pulse-level T₂ of 32–340 µs — a discrepancy of 3–11×. We introduce five experimental demonstrations showing K–R circuit-level diagnostics detect degradation invisible to T₁/T₂, provide higher temporal sensitivity, enable algorithm failure prediction, and confirm the theoretical prediction αₜ v ₜᶜʰ + αₑₜₕₒ = 2 within 7% on real hardware. These findings establish circuit-level K–R diagnostics as a necessary complement to pulse-level calibration for operational quantum computing.
We report the first experimental validation of a scalable, non-invasive quantum processor diagnostic system at 64-qubit scale. The TRUE Zigzag protocol characterizes T1 and T2 coherence properties of all target qubits simultaneously within a single job execution, producing a complete qubit health map from only three job submissions. Tested on IBM Quantum's ibm_fez backend (8,192 shots), the system graded all 64 qubits from EXCELLENT to UNSTABLE with baseline-to-after stability of 0.985→0.985, confirming non-invasive operation. Central discovery — Decreasing Scaling Law: Average diagnostic disturbance measured 0.252% at 8 qubits, 0.146% at 32 qubits, and 0.148% at 64 qubits, representing 92.7% improvement over linear scaling predictions. The 64Q/32Q ratio of 1.01× demonstrates plateau behavior, indicating no accuracy loss at arbitrarily larger scales. All three IBM Quantum Job IDs are publicly disclosed for independent verification. Full per-qubit data (CSV), experimental metadata (JSON), and visualization (PNG) are included. Patent: KR 10-2025-0180416
Abstract Early-stage venture screening requires navigating non-linear compensatory trade-offs that linear scoring models struggle to capture. We propose HQDIS, a parsimonious 4-qubit Variational Quantum Circuit (13 parameters) for a stylized version of this problem, conceptually motivated by a published study of Canadian venture investors (Bachher, Díaz de León, and Guild, 1999). Calibration uses a synthetic N = 45 benchmark (Benchmark A) authored by the researchers, not real historical decisions. We introduce a monotonic angular-scaling protocol (π/4) that provably prevents a phase-inversion aliasing failure in a common feature map. Under Repeated Stratified 5-Fold Cross-Validation (100 repeated resampling runs over the same 45 cases, not 100 independent samples), HQDIS attains 80.33% (± 2.72%, 95% CI) accuracy, statistically indistinguishable from Random Forest and Gradient Boosting (Nadeau–Bengio p > 0.7); Logistic Regression attains a nominally higher 91.56% (p = 0.133, d=-0.77), a gap our tests lack power to confirm at N = 45. Ablation shows a nominal 7-point gap and a medium effect size (d ≈ 0.51) between the full circuit and variants lacking ansatz entanglement, but the formal paired test does not reach significance (p ≈ 0.32) at this sample size. We execute Benchmark A on IBM's 156-qubit Heron processor (ibm_fez), obtaining 93.33% hardware accuracy and 97.78% concordance with simulation (κ = 0.9552; r = 0.9943) — a measure of hardware-simulation fidelity, not predictive validity. A counterfactual sweep on one boundary case demonstrates a reproducible auditability mechanism. In a second, explicitly synthetic benchmark (Benchmark B) built to favor non-linear rules, Logistic Regression significantly outperformed HQDIS in accuracy (paired p = 0.025) across 10 seeds, while HQDIS showed a non-significant nominal AUC-ROC advantage (paired p = 0.141); Random Forest significantly exceeded HQDIS on both metrics. We report this mixed result in full. We discuss the resulting, circumscribed implications for quantum decision-support architectures and report Benchmark A's synthetic construction as a central scope limitation.
We report three experimental tests of Unified Structural Theory (UST) predictions on IBM quantum hardware (ibm_fez and ibm_marrakesh, 156-qubit Heron r3 processors, March 16-17, 2026). (1) The UST T₁ predictor predicted 51 μs for the assigned Nb transmon qubit; measured value was 48.1 μs (6.0% error). (2) Crystal coupling topology based on I4/mmm layered structure improved W-state protection by 2.4× at N=3 qubits; gate overhead dominated at N≥9, demonstrating that native crystal coupling is required for scalable protection. (3) A variational quantum neural network (5 qubits, 30 parameters) trained on XOR achieved 100% accuracy on real hardware with 91% average confidence and 0.82 output separation. Channeled decoherence (mimicking crystal drain layers) produced lower training loss than noiseless operation, demonstrating that structured decoherence acts as computational regularization. All results obtained on hardware not owned, operated, or calibrated by the author.
As quantum processors scale beyond 100 qubits, distinguishing software bugs from stochastic hardware noise becomes a critical diagnostic challenge. We present a neuro-fuzzy framework that addresses this attribution problem by combining Adaptive Neuro-Fuzzy Inference Systems (ANFIS) with physics-grounded feature engineering. We introduce the Bhattacharyya veto, a hard constraint calibrated to the empirically characterized noise floor of the device, which classifies as buggy any output distribution whose divergence from the ideal exceeds what the device's noise produces under normal operation. The framework is validated on two IBM Heron r2 processors. On ibm_fez, across 105 circuits spanning 17 algorithm families, it attains 89.5% accuracy (Wilson 95% CI [82.2, 94.0]) with no abstentions; every residual error is a bug whose ideal computational-basis distribution is identical to the intended circuit's, or whose divergence lies below the device's noise floor. On a held-out suite of 30 deeper circuits (ISA depth to 100) executed on ibm_kingston, with all thresholds frozen, it attains 96.7% effective and 93.3% strict accuracy. We resolve key ambiguities - such as distinguishing correct Grover amplification from bug-induced collapse - and identify fundamental limits of single-basis diagnostics, including a Z-basis blind spot where phase-only errors remain statistically invisible. The extracted rule base is analyzed rather than asserted: the learned rules reproduce the physics of the veto, of the Grover boundary, and of depth-dependent noise without any of them being hard-coded. This work establishes an interpretable diagnostic layer that prevents error mitigation from being applied to logically flawed circuits.