Superconducting qubit performance is commonly assessed using snapshot calibration metrics such as coherence time (T2) and readout error probability. While useful for short-term characterization, such static representations obscure temporal structure present in long-term device operation. This technical note presents a time-resolved empirical analysis of publicly available calibration data from the IBM Quantum Athens superconducting quantum processor. By treating calibration records as a chronologically ordered time series, the analysis reveals recurring temporal alignment between abrupt coherence collapses and short-lived bursts of elevated readout error. The analysis is descriptive and model-agnostic by design. No microscopic noise sources, control mechanisms, or causal relationships are inferred. The observations are restricted to pre–error-correction behavior and are intended to document non-stationary, structured behavior that is obscured when calibration data are interpreted solely as static snapshots. These observations are relevant for scheduling, benchmarking, and any methodology that assumes stationary calibration parameters.
Superconducting qubit performance is commonly assessed using snapshot calibration metrics such as coherence time (T2) and readout error probability. While useful for short-term characterization, such static representations obscure temporal structure present in long-term device operation. This technical note presents a time-resolved empirical analysis of publicly available calibration data from the IBM Quantum Athens superconducting quantum processor. By treating calibration records as a chronologically ordered time series, the analysis reveals recurring temporal alignment between abrupt coherence collapses and short-lived bursts of elevated readout error. The analysis is descriptive and model-agnostic by design. No microscopic noise sources, control mechanisms, or causal relationships are inferred. The observations are restricted to pre–error-correction behavior and are intended to document non-stationary, structured behavior that is obscured when calibration data are interpreted solely as static snapshots. These observations are relevant for scheduling, benchmarking, and any methodology that assumes stationary calibration parameters.
This whitepaper identifies execution-time phase exposure as a missing diagnostic layer in quantum circuit evaluation. Quantum circuit performance is commonly evaluated through aggregate quantities such as gate count, circuit depth, total idle time, calibration data, error rates, and hardware coherence parameters such as T1 and T2. These quantities are necessary, but they do not identify when a qubit is actually carrying phase-sensitive quantum information whose preservation matters to the intended readout. The central observation is that idle time is not uniformly harmful. Idle time becomes consequential when it overlaps an active phase-bearing execution window: an interval in which phase-sensitive structure exists, persists, and remains relevant to a later readout. The whitepaper frames this distinction from a compact-fiber readout perspective and reports sanitized aggregate validation results from contemporary superconducting quantum hardware. The validation supports the claim that circuits with similar aggregate metrics can differ in observed performance because their idle intervals occur in different execution-time locations relative to phase-bearing structure. This record contains the whitepaper PDF only. It does not include circuit definitions, job identifiers, report schemas, implementation details, raw validation artifacts, or non-public workflow material.
Developing fault-tolerant quantum processors with error correction demands large arrays of physical qubits whose key performance metrics (coherence times, control fidelities) must remain within specifications over both short and long timescales. Here we investigated the temporal stability of subtractively fabricated CMOS-compatible superconducting transmon qubits. During a single cooldown and over a period of 95 hours, we monitored several parameters for 8 qubits, including coherence times T1 and T2∗, which exhibit fluctuations originating primarily from the interaction between two-level system (TLS) defects and the host qubit. We also demonstrate that subtractively-fabricated superconducting quantum devices align with the theoretical predictions that higher mean lifetimes T1 correspond to larger fluctuations. To assess long-term stability, we tracked two representative qubits over 10 cooldown cycles spanning more than one year. We observed an average total downward shift in both qubit transition frequencies of approximately 61 MHz within the thermal cycles considered. In contrast, readout resonator frequencies decreased only marginally. Meanwhile, T1 exhibits fluctuations from cycle to cycle, but maintains a stable baseline value.
Superconducting qubit parameters drift on sub-second timescales, motivating calibration and benchmarking techniques that can be executed on millisecond timescales. We demonstrate an on-FPGA workflow that co-locates pulse generation, data acquisition, analysis, and feed-forward, eliminating CPU round trips. Within this workflow, we introduce sparse-sampling and on-FPGA inference tools, including computationally efficient methods for estimation of exponential and sine-like response functions, as well as on-FPGA implementations of Nelder-Mead optimization and golden-section search. These methods enable low-latency primitives for readout calibration, spectroscopy, pulse-amplitude calibration, coherence estimation, and benchmarking. We deploy this toolset to estimate T1 in 10 ms, optimize readout parameters in 100 ms, optimize pulse amplitudes in 1 ms, and perform Clifford randomized gate benchmarking in 107 ms on a flux-tunable superconducting transmon qubit. Running a closed-loop on-FPGA recalibration protocol continuously for 6 hours enables more than 74,000 consecutive recalibrations and yields gate errors that consistently retain better performance than the baseline initial calibration. Correlation analysis shows that recalibration suppresses coupling of gate error to control-parameter drift while preserving a coherence-linked performance. Finally, we quantify uncertainty versus time-to-decision under our sparse sampling approaches and identify optimal parameter regimes for efficient estimation of qubit and pulse parameters.
Quantum computing holds the promise of transforming computational paradigms across science and engineering. But realizing potential on near term hardware demands on understanding of the noise processes that corrupt quantum circuit outputs. On superconducting processors, fragile qubits are continuously subjected to environmental disturbances including T1 relaxation, charge noise, and magnetic flux drift that cause measurement statistics to evolve in a nonstationary manner across repeated circuit executions, undermining the reliability of any result aggregated over a long experimental session. In this work, we treat the sequence of bitstring count outcomes from repeated executions of a fixed quantum circuit as a time series and conduct a systematic statistical investigation of its structure. The first contribution is constructing a predictive model of circuit output, demonstrating that future measurement outcomes can be forecast by exploiting temporal correlations in the execution record. We then extend the analysis to two circuits sharing the same physical qubit, examining cross-series dependencies and evaluating whether the drift behavior of one circuit can inform predictions about the other. The temporal structure of the signals is characterized in depth. The other contribution of this dissertation is to perform Wavelet-based multifractal analysis to reveal that quantum circuit outputs exhibit genuine multifractality. This is a hallmark of long range correlated, scale free processes rather than the simple Gaussian white noise assumed by standard error models. Complementary frequency-domain analysis identifies a residual 1/f noise component that persists after linear detrending, consistent with charge and flux noise mechanisms well documented in superconducting qubit literature. Motivated by these findings, The other contribution is to design and evaluate a suite of drift-mitigation filters including piecewise Huber regression, rolling median, smoothing spline, and Savitzky–Golay approaches under a rigorous chronological train/test protocol that mimics real operational deployment. The smoothing spline and median filter achieve near-zero corrected bias, while the rolling median emerges as the preferred solution for online, shot-by-shot correction due to its causal update structure and maximal robustness to impulsive hardware events. Taken together, our results characterize quantum circuit outputs as non-stationary, multifractal processes exhibiting long memory, seasonality, and inter-circuit causality, and establish a principled filtering framework for mitigating temporal bias drift in NISQ era quantum hardware.
TSR-Q-1 presents a preregistered and falsifiable experimental protocol designed to test for structured late-time coherence residuals in superconducting transmon qubits. The protocol does not treat generic recoherence, non-exponential decay, or non-Markovian behavior as evidence for the proposed framework, since such phenomena may arise from conventional open-system mechanisms. Instead, it targets a specific normalized temporal scaling law, tₙ/T₂ = nᵏ, with the preregistered theoretical value k* = 1.4706, corresponding to the first two target locations t₂/T₂ = 2.7714 and t₃/T₂ = 5.0310. If the associated amplitude-scaling hypothesis is retained, the predicted ratio is A₃/A₂ ≈ 0.551. The accompanying computational validation package develops the analysis pipeline through five stages: preliminary signal injection, blind null testing, blind injection-recovery, multi-qubit global-k inference, and sensitivity mapping. The synthetic null models include stretched-exponential decay, 1/f^α correlated noise, random-telegraph/TLS-like contributions, slow drift, white noise, and device-to-device variability. These simulations validate the detectability, specificity, and sensitivity of the proposed analysis procedure under the tested synthetic noise families. They do not constitute experimental evidence for the existence of the predicted physical effect. The next stage is a preregistered hardware implementation using superconducting qubits, with device-specific null calibration, blind analysis, systematic controls, held-out replication, and, ultimately, independent experimental replication.
Multiple layers of the quantum system full-stack require data on temporal variations in error rates of physical elements. The absence of this information, especially when users access cloud-based quantum systems with waiting queues between compilation and execution, can lead to unreliable computations due to outdated calibration data. One example is the compilation process that impacts the success rate of quantum circuits. This paper proposes using five machine learning and time-series models to predict error rate variability for two-qubit gates based on calibration data. We compare model accuracy and complexity in terms of execution time. The predicted information is applied to a noise-aware compiler to evaluate the impact on success rate. Experimental results on a real superconducting quantum processor demonstrate accurate predictions of temporal error rate variability, achieving performance comparable to that of real calibration data, reducing the impact of queue waiting times that can reach up to two days.