The superconducting transistor, or Josephson Field Effect Transistor (JoFET), is a versatile building block for ultra-low-power and high-energy-efficiency classical and quantum electronics. In a JoFET, the superconducting (zero-resistance) current is controlled by electrostatic gate voltage, which enables the scalability of solid-state quantum computers and the creation of next-generation superconducting integrated circuits (ICs). The development of JoFETs has so far been limited to single devices or a few-transistor circuits due to the lack of reproducible technological platform. Here, we report on technological progress of wafer-scale JoFET fabrication, achieving a 98% yield on a 150 mm wafer platform. Now that the large-scale and reproducible fabrication JoFETs has become feasible, we present behavioral and physics models as the required steps toward the design of novel JoFET-based ICs. Using the presented models, we obtain a good description of experimental data, thus paving the way for the design of next-generation superconducting ICs.
The superconducting transistor, or Josephson Field Effect Transistor (JoFET), is a versatile building block for ultra-low-power and high-energy-efficiency classical and quantum electronics. In a JoFET, the superconducting (zero-resistance) current is controlled by electrostatic gate voltage, which enables the scalability of solid-state quantum computers and the creation of next-generation superconducting integrated circuits (ICs). The development of JoFETs has so far been limited to single devices or a few-transistor circuits due to the lack of reproducible technological platform. Here, we report on technological progress of wafer-scale JoFET fabrication, achieving a 98% yield on a 150 mm wafer platform. Now that the large-scale and reproducible fabrication JoFETs has become feasible, we present behavioral and physics models as the required steps toward the design of novel JoFET-based ICs. Using the presented models, we obtain a good description of experimental data, thus paving the way for the design of next-generation superconducting ICs.
Scalability in the fabrication and operation of quantum computers is key to move beyond the NISQ era. So far, superconducting transmon qubits based on aluminum Josephson tunnel junctions have demonstrated the most advanced results, though this technology is difficult to implement with large-scale facilities. An alternative "gatemon" qubit has recently appeared, which uses hybrid superconducting/semiconducting (S/Sm) devices as gate-tuned Josephson junctions. Current implementations of these use nanowires however, of which the large-scale fabrication has not yet matured either. A scalable gatemon design could be made with CMOS Josephson Field-Effect Transistors as tunable weak link, where an ideal device has leads with a large superconducting gap that contact a short channel through high-transparency interfaces. High transparency, or low contact resistance, is achieved in the microelectronics industry with silicides, of which some turn out to be superconducting. The first part of the experimental work in this thesis covers material studies on two such materials: V3Si and PtSi, which are interesting for their high Tc, and mature integration, respectively. The second part covers experimental results on 50 nm gate length PtSi transistors, where the transparency of the S/Sm interfaces is modulated by the gate voltage. At low voltages, the transport shows no conductance at low energy, and well-defined features at the superconducting gap. The barrier height at the S/Sm interface is reduced by increasing the gate voltage, until a zero-bias peak appears around zero drain voltage, which reveals the appearance of an Andreev current. The successful gate modulation of Andreev current in a silicon-based transistor represents a step towards fully CMOS-integrated superconducting quantum computers.
Superconducting field-effect transitor (SuFET) and Josephson field-effect transistor (JoFET) technologies take advantage of electric-field-induced control of charge-carrier concentration to modulate the channel superconducting properties. Despite the fact that the field-effect is believed to be ineffective for superconducting metals, recent experiments showed electric-field-dependent modulation of the critical current ( I C ) in a fully metallic transistor. However, the grounding mechanism of this phenomenon is not completely understood. Here, we show the experimental realization of Ti-based Dayem bridge field-effect transistors (DB–FETs) able to control the I C of the superconducting channel. Our easy fabrication process for DB–FETs show symmetric full suppression of I C for applied critical gate voltages as low as V G C ≃ ±8 V at temperatures reaching about the 85% of the record critical temperature, T C ≃ 550 mK, for titanium. The gate-independent T C and normal-state resistance ( R N ) coupled with the increase of resistance in the superconducting state ( R S ) for gate voltages close to the critical value ( V G C ) suggest the creation of field-effect induced metallic puddles in the superconducting sea. Our devices show extremely high values of transconductance (| g m MAX | ≃ 15 μA/V at V G ≃ ±6.5 V) and variations of Josephson kinetic inductance ( L K ) with V G of 2 orders of magnitude. Therefore, the DB–FET appears as an ideal candidate for the realization of superconducting electronics, superconducting qubits, and tunable interferometers as well as photon detectors.
In the upcoming decades quantum technologies, especially quantum computation, will have a strong influence on industrial, technological, economic, and social progress and are, therefore, considered to be one of the key technologies. The fundamental building blocks for quantum computation are quantum bits (qubits). The superconducting platform offers one of the most promising implementations due to its monolithic character and potential for scalability. Present research around the world primarily focusses on scaling up the number of qubits, so reliable wafer-scale fabrication technologies are mandatory. In this paper, we present our recent developments on wafer-scale fabrication of superconducting quantum circuits including Josephson junctions by the Manhattan-type technology. We discuss fabrication parameters as well as electrical characterization. For arrays out of 50 Josephson junctions with structure dimensions of 200 nm × 200 nm, we achieve a critical current standard deviation of approx. 3% on-chip and 7% on-wafer. We also show first measurement results of so fabricated transmon-type qubits with relaxation and decoherence times ofT1= 12.5 µs andT2= 15.0 µs, respectively. With an increasing number of superconducting qubits and, thus, their input and read-out lines, new challenges arise: Crosstalk between qubits, unwanted modes in the qubit environment, and required interconnections. One way to counteract is the implementation of low inductance connections across coplanar waveguides. This can be realized by aluminum air bridges. In this paper we discuss the air bridges’ fabrication parameters and the impact on the integrated circuits’ elements, e.g., Josephson junctions. We show electrical and superconducting measurements with critical temperatures and critical currents ofTc> 1.0 K andIc> 0.6 mA, respectively.
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra energy efficient data conversion architectures that remain functional at deep cryogenic temperatures.In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a novel quantum enhanced Josephson junction field effect transistor (JJFET).Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current controlled superconducting devices while aligning naturally with CMOS style design methodologies.Building on our previously developed Verilog A compact model calibrated to experimental data, we design and simulate a three bit JJFET based flash ADC.The core comparator block is realized through careful bias current selection and augmented with a three terminal nanocryotron to precisely define reference voltages.Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic level restoration across stages.Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage driven superconducting mixed signal circuits.This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum classical co-processors, low-power AI accelerators, and next generation energy constrained computing platforms.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
Superconducting quantum computing has demonstrated exponential improvements in coherence times over the past two decades, bringing us to the present Noisy Intermediate Scale Quantum (NISQ) era. Improvements in materials and fabrication techniques are still required along with circuit and algorithm innovations to move beyond the NISQ era. We discuss several aspects of the process development work that enables the fabrication of superconducting quantum devices and circuits at 300 mm wafer scale, using materials, processes and tools that are entirely compatible with high-volume integrated circuit fabs. Damascene structures of superconducting tantalum and aluminum (embedded in high resistivity silicon substrates) are described along with examples of process control. The use of such structures for coplanar waveguide resonators in quantum circuits is described, along with modifications to enable integration of normal metal traps to mitigate quasiparticle poisoning. This paper also includes a description of the considerable process development required to enable ALD-TaN based Josephson junctions fabricated with entirely 300 mm compatible processes, in contrast to the lift-off based processes currently in wide use for qubit fabrication. It concludes with a description of how these efforts help with establishing a Quantum Foundry at NY CREATES (a non-profit organization) that can democratize access to advanced qubit fabrication by offering an open superconducting quantum Process Design Kit (PDK).