System-Level Comparison of Superconductor-Semiconductor Interface Circuits
Keith Krause, Yerzhan Mustafa, Archit Shah, Christopher J. Lewis, Chase C. Tillman, Tara Renduchintala, Mingye Li, Sasan Razmkhah, Michael C. Hamilton, Murali Annavaram, Selçuk Köse, Massoud Pedram
Cryogenic computing systems often require communication between single flux quantum (SFQ) circuits at 4 K and CMOS circuits at a higher temperature stage. Interface circuits such as a 4JL (four-junction logic) gate and a SQUID (superconducting quantum interference device) stack have previously been used for SFQ-CMOS data links, but they have only been used for systems contained at 4 K. When communicating with CMOS circuits at a higher temperature stage, these interface circuits must be implemented in accordance with a holistic analysis of the entire cryogenic computing system. We have conducted an analysis in which we compare the impact of a 4JL gate and a SQUID stack on a system designed for the HYPRES ICE-T. For our analysis, we use the CORE e4 RSFQ microprocessor as the SFQ circuitry at 4 K. We provide guidelines for deciding between a 4JL gate and a SQUID stack as superconductor-semiconductor interface circuits in hybrid computing systems with multiple temperature stages.
Cryogenic computing systems often require communication between single flux quantum (SFQ) circuits at 4 K and CMOS circuits at a higher temperature stage. Interface circuits such as a 4JL (four-junction logic) gate and a SQUID (superconducting quantum interference device) stack have previously been used for SFQ-CMOS data links, but they have only been used for systems contained at 4 K. When communicating with CMOS circuits at a higher temperature stage, these interface circuits must be implemented in accordance with a holistic analysis of the entire cryogenic computing system. We have conducted an analysis in which we compare the impact of a 4JL gate and a SQUID stack on a system designed for the HYPRES ICE-T. For our analysis, we use the CORE e4 RSFQ microprocessor as the SFQ circuitry at 4 K. We provide guidelines for deciding between a 4JL gate and a SQUID stack as superconductor-semiconductor interface circuits in hybrid computing systems with multiple temperature stages.
Digital communication between temperature stages is a critical part of superconducting electronics systems. Specifically, enabling clean, low-loss communication between single flux quantum (SFQ) circuits at 4 K and CMOS circuitry and memory at higher temperature stages (such as 50 K) can allow for significantly more system memory than what current superconducting devices and memories allow. An amplifier for SFQ pulses, such as a four-junction logic (4JL) gate, must also be included at the beginning of the data link. We have simulated such a data link in Pathwave ADS, which uses four-junction logic (4JL) gate characteristics that were initially simulated in JoSIM. ANSYS HFSS was used to generate the S-parameters used in ADS. Eye diagrams generated from the ADS simulation results are analyzed. The eye diagrams from the data link give an eye width of 77.2 ps and an eye height of 2.16 mV in the worst case, compared to an eye width of 94.3 ps and an eye height of 4.24 mV from the 4JL gate. These simulations will enable future hardware implementations of SFQ to CMOS memory data links.
Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.
Superconductor-semiconductor interface circuits are integral part of connecting cryogenic classical and quantum computing systems with the room temperature electronics. Due to the cooling power constraints of cryogenic setups, the number of data transmission channels between temperature stages is often limited by the heat load of cables and connectors. As a result, a high data rate (throughput) per channel is desired for large-scale computing systems. The state-of-the-art superconductor-semiconductor interface circuits use a binary data format. In this work, a novel interface circuit is proposed that produces signals with pulse-amplitude modulation (PAM). As a case study, a PAM-4 SQUID (superconducting quantum interference device) stack interface circuit is developed. With four output voltage levels, the effective data rate can be doubled while keeping the same operating frequency. Alternatively, the number of cryogenic cables can be reduced by two times as compared to the conventional binary data links.
Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10-12. We will discuss the trade-off among circuit robustness, speed, and power consumption.
Abstract The many advantages of cryogenically cooled single-flux quantum (SFQ) circuits imply that the high speed and low voltage output signals must be amplified and interfaced with standard electronics. State-of-the-art low-noise and wide-band amplifiers are required to interface with room temperature electronics. One solution is to place preamplifiers at the cryogenic stage, which requires specific semiconductor design and fabrication. However, a more viable and energy-efficient approach is to integrate the pulsed logic circuit output stages with on-chip superconductor preamplifiers. We designed, fabricated, and tested an on-chip compact voltage multiplier integrated with the output stage of SFQ circuits to increase the voltage amplitude of SFQ pulses. The circuit is designed with the same technology as the logic circuit hence its noise level is lower, and it works at higher frequencies compared to complementary metal-oxide semi-conductor amplifiers and due to quantized nature of it there is no added noise. The fabricated circuit has a compact size of 160 µ m × 320 µ m and provides about 10 dB gain with measured 600 µ V output voltage at frequencies up to ∼25 GHz in simulations. By stacking more levels, over 20 dB gain at circuit level is achievable as shown in simulations. Moreover the gain of the superconductor voltage amplifier is quantized and programmable.
Improving the efficiency in digital data transport, originating from 4 K superconductor integrated circuits (ICs) to standard room-temperature (300 K) electronics, both in terms of speed and power consumption, is vitally important for nearly all applications of superconductor digital electronics. The required data link must include all necessary amplification and conditioning to convert digital data from single flux quantum (SFQ) logic to standard CMOS logic levels. Therefore, one must minimize the overall power consumption for the required total data throughout by taking into account all parts of the link: (1) data transmitters or output drivers with SFQ input, (2) additional amplifiers, (3) transmission lines, and (4) data receivers at room-temperature, such as the ones available on commercial field-programmable gate arrays (FPGAs). Here, we describe two variants of electrical data links, with and without cryogenic semiconductor amplifiers.