Semiconductor quantum dots have shown impressive breakthroughs in the last years, with single and two qubit gate fidelities matching other leading platforms and scalability still remaining a relative strength. However, due to qubit wiring considerations, mobile electron architectures have been proposed to facilitate upward scaling. In this work, we examine and demonstrate the possibility of significantly outperforming static EDSR-type single-qubit pulsing by taking advantage of the larger spatial mobility to achieve larger Rabi frequencies and reduce the effect of charge noise. Our theoretical results indicate that fidelities are ultimately bottlenecked by spin-valley physics, which can be suppressed through the use of quantum optimal control, and we demonstrate that, across different potential regimes and competing physical models, shuttling based single-qubit gates retain significant advantage over existing alternatives.
Semiconductor quantum dots have shown impressive breakthroughs in the last years, with single and two qubit gate fidelities matching other leading platforms and scalability still remaining a relative strength. However, due to qubit wiring considerations, mobile electron architectures have been proposed to facilitate upward scaling. In this work, we examine and demonstrate the possibility of significantly outperforming static EDSR-type single-qubit pulsing by taking advantage of the larger spatial mobility to achieve larger Rabi frequencies and reduce the effect of charge noise. Our theoretical results indicate that fidelities are ultimately bottlenecked by spin-valley physics, which can be suppressed through the use of quantum optimal control, and we demonstrate that, across different potential regimes and competing physical models, shuttling based single-qubit gates retain significant advantage over existing alternatives.
There have been impressive breakthroughs in semiconductor quantum dots in recent years, with single- and two-qubit gate fidelities matching other leading platforms and scalability still remaining a relative strength; however, due to qubit wiring considerations, mobile electron architectures have been proposed to facilitate upward scaling, and this opens the possibility of enlarging the motional amplitude for electric-dipole spin resonance (EDSR)-based qubit manipulation. In this work, we examine and demonstrate the possibility of significantly outperforming static-EDSR-type single-qubit pulsing by taking advantage of greater spatial mobility to achieve higher Rabi frequencies and reduce the effect of charge noise. Our theoretical results indicate that fidelities are ultimately bottlenecked by spin-valley physics, which can be suppressed through the use of quantum optimal control. We demonstrate that, across different potential regimes and competing physical models, shuttling-based single-qubit gates retain significant advantages over existing alternatives.
Single spin quantum dot qubits in silicon are a promising candidate for a scalable quantum processor due to their long coherence times, compact size, and ease of integration into existing fabrication technologies. Realizing a large quantum processor composed of thousands or more logical qubits requires the integration of conventional transistor circuitry \nand wiring interconnects to control each individual dot in the processor. The high density of control wiring required for these processors presents many engineering challenges. In this thesis, we propose a surface code quantum processor for silicon quantum dot qubits based on a node/network architecture. Local nodes consisting of just seven quantum dots are \nspatially separated on the order of microns to facilitate space for the necessary high density wiring. Entanglement is distributed between individual nodes via shuttling of entangled electron pairs throughout the network. X or Z stabilizer operations, necessary for operating the surface code, are realized by distributing three electron spin singlet pairs across four local nodes followed by local gate operations and ancilla measurements. Simulations of electron shuttling indicate that adiabatic transport is possible on timescales that do not bottleneck the processor speed. Phase rotation of the shuttled spin, induced by the Stark shift, can lower the overall shuttling fi delity; however, the error can be mitigated by proper electrostatic tuning of the stationary electron's g-factor. Using realistic noise models, we estimate error thresholds with respect to single and two-qubit gate fidelities as well as \nsinglet dephasing errors during shuttling. Electron shuttling is a key resource of the proposed network architecture. We continue the shuttling simulations by presenting an algorithm for finding constant-adiabatic shuttling control pulses, which enables a more rigorous study of how different conditions impact the shuttling speed and fidelity. These constant adiabatic pulses are used to optimize the physical device geometry to maximize charge shuttling speeds up to 300 nm/ns in the single-valley case. We then switch to an effective Hamiltonian representation where spin and valley degrees of freedom are accounted for during shuttling. Using realistic device and material parameters, shuttle speeds in the range 10-100 nm/ns with high spin entanglement \n fidelities are obtained when the tunneling energy exceeds the Zeeman energy. High fidelity shuttling also requires the inter-dot valley phase difference to be below a threshold determined by the ratio of tunneling and Zeeman energies, so that spin-valley-orbit mixing is weak. In this regime, we find that the primary source of infi delity is a coherent spin rotation that is correctable, in principle, using single spin rotations. Two-qubit gates in the network architecture are mediated by the exchange interaction, \nan interaction that stems from the Coulomb interaction but manifests as a rotation between the |0,1> and |1,0> two qubit states. Realizing fault tolerant two-qubit gates has proven difficult in silicon quantum dots due to charge noise which perturbs the electron orbitals states, causing decoherence. Quantitatively accurate modelling of exchange in general quantum dot networks is important towards realizing fault tolerant gates. Traditional modelling methods, such as a full con figuration interaction approach, are cumbersome due to significant computational overhead required when accounting for the electron-electron interactions in the calculation. We present a modi ed linear combination of harmonic orbitals con figuration interaction (LCHO-CI) approach which signifi cantly reduces the computational time for obtaining quantitatively accurate estimations of exchange. The method works by approximating the single electron orbitals of the quantum dot network using an orthogonal basis of harmonic orbitals. This choice of orthogonal basis allows a precalculated library of matrix elements to be used in evaluating the Coulomb interactions, which speeds up the LCHO-CI calculation. The modi ed LCHO-CI approach is then used to study how the physical device geometry impacts the charge noise sensitivity of a double quantum dot system. We fi nd that, in general, geometries which increase the dot charging energy and decrease the gate lever arms improve the system's sensitivity to charge noise. We conclude this thesis by pivoting away from theoretical studies of silicon quantum dots and towards experimental studies of electron transport in dopant-free GaAs heterostructures. In modulation doped GaAs heterostructures, a doping layer is used to induce a two-dimensional electron gas (2DEG) at the heterojunction. Dopant-free GaAs lack the doping layer which makes fabrication more difficult as local electron reservoirs must be used to bring carriers and induce a 2DEG. The lack of the doping layer offers several advantages over modulation doped heterostructures, such as gate-ability of the 2DEG and ability to make ambipolar devices (both n- and p-type ohmic contacts). Realizing n- and p-type ohmic contacts requires etching a recess pit and depositing the ohmic material at an angle in order to preventing screening of the top gate when inducing a 2DEG or two-dimensional hole gas (2DHG). Magnetotransport experiments are used to characterize an induced 2DEG and 2DHG in a Hall bar fabricated on a 310 nm deep single heterojunction. The carrier mobility and density can be tuned using the top gate, and we achieve peak mobility values of 4.5E6 cm2/Vs and 0.65E6 cm2/Vs for the 2DEG and 2DHG respectively. We then move to a one-dimensional system and study electron transport through a quantum point contact. Conductance quantization is observed, and subband spectroscopy \nmeasurements indicate a 1D subband spacing of 4.5 meV. Finally, we study dynamically driven electron transport in a zero-dimensional system using a tunable-barrier quantum dot acting as a single electron pump. Single electron pumping is observed up to T = 5 K, and fi ts to the electron cascade model suggests pumping errors of 1.87 ppm when operated at a driving frequency of f = 500 MHz.
Dynamic qubit routing is emerging as a promising architectural path for semiconductor quantum processors. Charge carriers can be rapidly moved around on a chip using traveling-wave potentials known as conveyors, preserving the spin state with high fidelity. Originally developed for spin transport, conveyor-mode shuttling may also offer opportunities for performing qubit operations directly controlled by the motion itself. Here, we demonstrate coherent single- and two-qubit control by conveyor-mode electron shuttling, using two conceptually different approaches. First, conveyor electric-dipole spin resonance (conveyor EDSR) achieves high-fidelity rotations by resonantly shuttling spins through transverse magnetic-field gradients at their mean Larmor frequency. Second, conveyor diabatic gates exploit quantization-axis tilts for tunable bang-bang control. Combining diabatic conveyor transport with exchange activation controlled by the motion directly yields a variety of effective two-qubit interactions selectable via the shuttling speed and distance. These experimental results motivate an architectural paradigm of reconfigurable and transport-driven spin qubits.
Quantum processor architectures must enable scaling to large qubit numbers while providing two-dimensional qubit connectivity and exquisite operation fidelities. For microwave-controlled semiconductor spin qubits, dense arrays have made considerable progress, but are still limited in size by wiring fan-out and exhibit significant crosstalk between qubits. To overcome these limitations, we introduce the SpinBus architecture, which uses electron shuttling to connect qubits and features low operating frequencies and enhanced qubit coherence. Device simulations for all relevant operations in the Si/SiGe platform validate the feasibility with established semiconductor patterning technology and operation fidelities exceeding 99.9%. Control using room temperature instruments can plausibly support at least 144 qubits, but much larger numbers are conceivable with cryogenic control circuits. Building on the theoretical feasibility of high-fidelity spin-coherent electron shuttling as key enabling factor, the SpinBus architecture may be the basis for a spin-based quantum processor that meets the scalability requirements for practical quantum computing.
Spin shuttling has crystalized as a powerful and promising tool for establishing intermediate-range connectivity in semiconductor spin-qubit devices. Although experimental demonstrations have performed exceptionally well on different materials platforms, the question of how to handle areas of low valley splitting in silicon during shuttling remains unresolved. In this work, we explore the possibility of utilizing the valley degree of freedom, particularly in regions of low valley splitting, to allow mobile spin qubits to be shuttled through an occupied stationary quantum dot, thereby leapfrogging over the stationary electron. This not only grants a more enriched mobility for shuttled electrons, as it opens new possible routing paths, but also enables the implementation of an entangling SWAPγ two-qubit gate operation in the process. Simulating this process for different sets of parameters, we demonstrate the feasibility of such an operation and offer a unique use case for otherwise precarious regions of a quantum processor chip and propose a possible extension to the set of possible operations for silicon spin qubit devices.
Mobile spin qubit architectures promise flexible connectivity for efficient quantum error correction and relaxed device layout constraints, but their viability rests on preserving spin coherence during transport. While shuttling transforms spatial disorder into time-dependent noise, its net impact on spin coherence remains an open question. Here we demonstrate systematic noise mitigation during spin shuttling in a linear 28Si/SiGe quantum dot device. First, by passively reducing magnetic field gradients, we minimize charge-noise coupling to the spin and double the spatially averaged dephasing time T2∗(xn) from 4.4 to 8.5μs. Next, we exploit motional narrowing by periodically shuttling the qubit, achieving a further enhancement in coherence time up to T2∗,sh=11.5μs. Finally, we incorporate dynamical decoupling techniques while periodically shuttling over distances exceeding 200nm, reaching T2H,sh=32μs. For the same setup, we demonstrate that dressed-state shuttling provides robust protection against low-frequency noise with a decay time TRsh=21μs, without the overhead of pulsed control and allowing protection during one-way spin transport. By preserving coherence over timescales exceeding typical gate and readout operations, the demonstrated strategies establish mobile spin qubits as a viable solution for scalable silicon quantum processors.