Single spin quantum dot qubits in silicon are a promising candidate for a scalable quantum processor due to their long coherence times, compact size, and ease of integration into existing fabrication technologies. Realizing a large quantum processor composed of thousands or more logical qubits requires the integration of conventional transistor circuitry \nand wiring interconnects to control each individual dot in the processor. The high density of control wiring required for these processors presents many engineering challenges. In this thesis, we propose a surface code quantum processor for silicon quantum dot qubits based on a node/network architecture. Local nodes consisting of just seven quantum dots are \nspatially separated on the order of microns to facilitate space for the necessary high density wiring. Entanglement is distributed between individual nodes via shuttling of entangled electron pairs throughout the network. X or Z stabilizer operations, necessary for operating the surface code, are realized by distributing three electron spin singlet pairs across four local nodes followed by local gate operations and ancilla measurements. Simulations of electron shuttling indicate that adiabatic transport is possible on timescales that do not bottleneck the processor speed. Phase rotation of the shuttled spin, induced by the Stark shift, can lower the overall shuttling fi delity; however, the error can be mitigated by proper electrostatic tuning of the stationary electron's g-factor. Using realistic noise models, we estimate error thresholds with respect to single and two-qubit gate fidelities as well as \nsinglet dephasing errors during shuttling. Electron shuttling is a key resource of the proposed network architecture. We continue the shuttling simulations by presenting an algorithm for finding constant-adiabatic shuttling control pulses, which enables a more rigorous study of how different conditions impact the shuttling speed and fidelity. These constant adiabatic pulses are used to optimize the physical device geometry to maximize charge shuttling speeds up to 300 nm/ns in the single-valley case. We then switch to an effective Hamiltonian representation where spin and valley degrees of freedom are accounted for during shuttling. Using realistic device and material parameters, shuttle speeds in the range 10-100 nm/ns with high spin entanglement \n fidelities are obtained when the tunneling energy exceeds the Zeeman energy. High fidelity shuttling also requires the inter-dot valley phase difference to be below a threshold determined by the ratio of tunneling and Zeeman energies, so that spin-valley-orbit mixing is weak. In this regime, we find that the primary source of infi delity is a coherent spin rotation that is correctable, in principle, using single spin rotations. Two-qubit gates in the network architecture are mediated by the exchange interaction, \nan interaction that stems from the Coulomb interaction but manifests as a rotation between the |0,1> and |1,0> two qubit states. Realizing fault tolerant two-qubit gates has proven difficult in silicon quantum dots due to charge noise which perturbs the electron orbitals states, causing decoherence. Quantitatively accurate modelling of exchange in general quantum dot networks is important towards realizing fault tolerant gates. Traditional modelling methods, such as a full con figuration interaction approach, are cumbersome due to significant computational overhead required when accounting for the electron-electron interactions in the calculation. We present a modi ed linear combination of harmonic orbitals con figuration interaction (LCHO-CI) approach which signifi cantly reduces the computational time for obtaining quantitatively accurate estimations of exchange. The method works by approximating the single electron orbitals of the quantum dot network using an orthogonal basis of harmonic orbitals. This choice of orthogonal basis allows a precalculated library of matrix elements to be used in evaluating the Coulomb interactions, which speeds up the LCHO-CI calculation. The modi ed LCHO-CI approach is then used to study how the physical device geometry impacts the charge noise sensitivity of a double quantum dot system. We fi nd that, in general, geometries which increase the dot charging energy and decrease the gate lever arms improve the system's sensitivity to charge noise. We conclude this thesis by pivoting away from theoretical studies of silicon quantum dots and towards experimental studies of electron transport in dopant-free GaAs heterostructures. In modulation doped GaAs heterostructures, a doping layer is used to induce a two-dimensional electron gas (2DEG) at the heterojunction. Dopant-free GaAs lack the doping layer which makes fabrication more difficult as local electron reservoirs must be used to bring carriers and induce a 2DEG. The lack of the doping layer offers several advantages over modulation doped heterostructures, such as gate-ability of the 2DEG and ability to make ambipolar devices (both n- and p-type ohmic contacts). Realizing n- and p-type ohmic contacts requires etching a recess pit and depositing the ohmic material at an angle in order to preventing screening of the top gate when inducing a 2DEG or two-dimensional hole gas (2DHG). Magnetotransport experiments are used to characterize an induced 2DEG and 2DHG in a Hall bar fabricated on a 310 nm deep single heterojunction. The carrier mobility and density can be tuned using the top gate, and we achieve peak mobility values of 4.5E6 cm2/Vs and 0.65E6 cm2/Vs for the 2DEG and 2DHG respectively. We then move to a one-dimensional system and study electron transport through a quantum point contact. Conductance quantization is observed, and subband spectroscopy \nmeasurements indicate a 1D subband spacing of 4.5 meV. Finally, we study dynamically driven electron transport in a zero-dimensional system using a tunable-barrier quantum dot acting as a single electron pump. Single electron pumping is observed up to T = 5 K, and fi ts to the electron cascade model suggests pumping errors of 1.87 ppm when operated at a driving frequency of f = 500 MHz.
Single spin quantum dot qubits in silicon are a promising candidate for a scalable quantum processor due to their long coherence times, compact size, and ease of integration into existing fabrication technologies. Realizing a large quantum processor composed of thousands or more logical qubits requires the integration of conventional transistor circuitry \nand wiring interconnects to control each individual dot in the processor. The high density of control wiring required for these processors presents many engineering challenges. In this thesis, we propose a surface code quantum processor for silicon quantum dot qubits based on a node/network architecture. Local nodes consisting of just seven quantum dots are \nspatially separated on the order of microns to facilitate space for the necessary high density wiring. Entanglement is distributed between individual nodes via shuttling of entangled electron pairs throughout the network. X or Z stabilizer operations, necessary for operating the surface code, are realized by distributing three electron spin singlet pairs across four local nodes followed by local gate operations and ancilla measurements. Simulations of electron shuttling indicate that adiabatic transport is possible on timescales that do not bottleneck the processor speed. Phase rotation of the shuttled spin, induced by the Stark shift, can lower the overall shuttling fi delity; however, the error can be mitigated by proper electrostatic tuning of the stationary electron's g-factor. Using realistic noise models, we estimate error thresholds with respect to single and two-qubit gate fidelities as well as \nsinglet dephasing errors during shuttling. Electron shuttling is a key resource of the proposed network architecture. We continue the shuttling simulations by presenting an algorithm for finding constant-adiabatic shuttling control pulses, which enables a more rigorous study of how different conditions impact the shuttling speed and fidelity. These constant adiabatic pulses are used to optimize the physical device geometry to maximize charge shuttling speeds up to 300 nm/ns in the single-valley case. We then switch to an effective Hamiltonian representation where spin and valley degrees of freedom are accounted for during shuttling. Using realistic device and material parameters, shuttle speeds in the range 10-100 nm/ns with high spin entanglement \n fidelities are obtained when the tunneling energy exceeds the Zeeman energy. High fidelity shuttling also requires the inter-dot valley phase difference to be below a threshold determined by the ratio of tunneling and Zeeman energies, so that spin-valley-orbit mixing is weak. In this regime, we find that the primary source of infi delity is a coherent spin rotation that is correctable, in principle, using single spin rotations. Two-qubit gates in the network architecture are mediated by the exchange interaction, \nan interaction that stems from the Coulomb interaction but manifests as a rotation between the |0,1> and |1,0> two qubit states. Realizing fault tolerant two-qubit gates has proven difficult in silicon quantum dots due to charge noise which perturbs the electron orbitals states, causing decoherence. Quantitatively accurate modelling of exchange in general quantum dot networks is important towards realizing fault tolerant gates. Traditional modelling methods, such as a full con figuration interaction approach, are cumbersome due to significant computational overhead required when accounting for the electron-electron interactions in the calculation. We present a modi ed linear combination of harmonic orbitals con figuration interaction (LCHO-CI) approach which signifi cantly reduces the computational time for obtaining quantitatively accurate estimations of exchange. The method works by approximating the single electron orbitals of the quantum dot network using an orthogonal basis of harmonic orbitals. This choice of orthogonal basis allows a precalculated library of matrix elements to be used in evaluating the Coulomb interactions, which speeds up the LCHO-CI calculation. The modi ed LCHO-CI approach is then used to study how the physical device geometry impacts the charge noise sensitivity of a double quantum dot system. We fi nd that, in general, geometries which increase the dot charging energy and decrease the gate lever arms improve the system's sensitivity to charge noise. We conclude this thesis by pivoting away from theoretical studies of silicon quantum dots and towards experimental studies of electron transport in dopant-free GaAs heterostructures. In modulation doped GaAs heterostructures, a doping layer is used to induce a two-dimensional electron gas (2DEG) at the heterojunction. Dopant-free GaAs lack the doping layer which makes fabrication more difficult as local electron reservoirs must be used to bring carriers and induce a 2DEG. The lack of the doping layer offers several advantages over modulation doped heterostructures, such as gate-ability of the 2DEG and ability to make ambipolar devices (both n- and p-type ohmic contacts). Realizing n- and p-type ohmic contacts requires etching a recess pit and depositing the ohmic material at an angle in order to preventing screening of the top gate when inducing a 2DEG or two-dimensional hole gas (2DHG). Magnetotransport experiments are used to characterize an induced 2DEG and 2DHG in a Hall bar fabricated on a 310 nm deep single heterojunction. The carrier mobility and density can be tuned using the top gate, and we achieve peak mobility values of 4.5E6 cm2/Vs and 0.65E6 cm2/Vs for the 2DEG and 2DHG respectively. We then move to a one-dimensional system and study electron transport through a quantum point contact. Conductance quantization is observed, and subband spectroscopy \nmeasurements indicate a 1D subband spacing of 4.5 meV. Finally, we study dynamically driven electron transport in a zero-dimensional system using a tunable-barrier quantum dot acting as a single electron pump. Single electron pumping is observed up to T = 5 K, and fi ts to the electron cascade model suggests pumping errors of 1.87 ppm when operated at a driving frequency of f = 500 MHz.
Abstract A design for a large-scale surface code quantum processor based on a node/network approach is introduced for semiconductor quantum dot spin qubits. The minimal node contains only seven quantum dots, and nodes are separated on the micron scale, creating useful space for wiring interconnects and integration of conventional transistor circuits. Entanglement is distributed between neighbouring nodes by loading spin singlets locally and then shuttling one member of the pair through a linear array of empty dots. A node contains one data qubit, two ancilla qubits, and additional dots to facilitate electron shuttling and measurement of the ancillas. A four-node GHZ state is realized by sharing three internode singlets followed by local gate operations and ancilla measurements. Further local operations produce an X or Z stabilizer on the four data qubits, which is the fundamental operation of the surface code. Electron shuttling is simulated in the single-valley case using a simple gate electrode geometry without explicit barrier gates, and demonstrates that adiabatic transport is possible on timescales that do not present a speed bottleneck to the processor. An important shuttling error in a clean system is uncontrolled phase rotation of the spin due to modulation of the electronic g -factor during transport, owing to the Stark effect. This error can be reduced by appropriate electrostatic tuning of the stationary electron’s g -factor. While these simulations are unrealistic in neglecting spin–orbit, valley and decoherence effects, they are realistic with respect to the gate-induced potential landscape and are a first step towards more realistic modelling. Using reasonable noise models, we estimate error thresholds with respect to single and two-qubit gate fidelities as well as singlet dephasing errors during shuttling. A twirling protocol transforms the non-Pauli noise associated with exchange gate operations into Pauli noise, making it possible to use the Gottesman–Knill theorem to efficiently simulate large codes.
Universal quantum computing promises solutions to a wide range of problems of significant scientific and socioeconomic impact that are computationally intractable using classical hardware. Since physical qubits are inherently noisy and prone to decoherence, realizing a sufficient number of logical qubits to unlock practically relevant problem classes will likely require quantum error correction, resulting in an overhead of millions of physical qubits. Among all competing hardware platforms, spin qubits in gate-defined quantum dots are uniquely positioned: single- and two-qubit gate fidelities routinely exceed the error-correction threshold, and the experimentally proven compatibility with industrial-grade semiconductor manufacturing may enable millions of qubits on a single chip. Realizing this potential, however, requires quantum processor architectures that scale to large qubit numbers with two‑dimensional connectivity while maintaining high operational fidelities. Building on the theoretical feasibility of high‑fidelity spin‑coherent electron shuttling, the SpinBus architecture is introduced to enable scaling to application-relevant qubit numbers. The SpinBus architecture leverages the conveyor-mode shuttling device named Quantum Bus (QuBus) for coherent qubit coupling over micron‑scale distances to accommodate, at the level of the quantum processor chip, wiring fan‑out and locally integrated control electronics at cryogenic temperatures. Device simulations for all relevant operations in the Si/SiGe platform validate operation fidelities exceeding 99 % as well as compatibility with the requirements of established semiconductor patterning technology. Control with room‑temperature electronics plausibly supports at least 144 qubits, while substantially larger quantum processor sizes are conceivable using cryogenic control electronics. For the experimental realization of QuBus devices, a novel high‑yield multilayer electron-beam lithography process, which can readily be adapted to different device layouts, was developed to fabricate the required > 100 aligned metallic gate electrodes. Benchmarking with a semiconductor industry‑inspired methodology and inspection of > 100 devices demonstrated 99 % gate fabrication yield and at least 5 nm overlay accuracy. Utilizing GaAs/(Al,Ga)As QuBus prototype devices with a 7 µm shuttling channel for quantized-current experiments validated key criteria for conveyor-mode shuttling, in particular linear current scaling for operation frequencies up to 40 MHz, and provided preliminary evidence consistent with quantized conveyor-mode electron transfer. These results support the viability of conveyor-mode shuttling for qubit coupling and indicate the suitability of QuBus devices for metrological applications.
The spin states of single electrons in gate-defined quantum dots satisfy crucial requirements for a practical quantum computer. These include extremely long coherence times, high-fidelity quantum operation, and the ability to shuttle electrons as a mechanism for on-chip flying qubits. To increase the number of qubits to the thousands or millions of qubits needed for practical quantum information, we present an architecture based on shared control and a scalable number of lines. Crucially, the control lines define the qubit grid, such that no local components are required. Our design enables qubit coupling beyond nearest neighbors, providing prospects for nonplanar quantum error correction protocols. Fabrication is based on a three-layer design to define qubit and tunnel barrier gates. We show that a double stripline on top of the structure can drive high-fidelity single-qubit rotations. Self-aligned inhomogeneous magnetic fields induced by direct currents through superconducting gates enable qubit addressability and readout. Qubit coupling is based on the exchange interaction, and we show that parallel two-qubit gates can be performed at the detuning-noise insensitive point. While the architecture requires a high level of uniformity in the materials and critical dimensions to enable shared control, it stands out for its simplicity and provides prospects for large-scale quantum computation in the near future.
Semiconductor quantum dots have shown impressive breakthroughs in the last years, with single and two qubit gate fidelities matching other leading platforms and scalability still remaining a relative strength. However, due to qubit wiring considerations, mobile electron architectures have been proposed to facilitate upward scaling. In this work, we examine and demonstrate the possibility of significantly outperforming static EDSR-type single-qubit pulsing by taking advantage of the larger spatial mobility to achieve larger Rabi frequencies and reduce the effect of charge noise. Our theoretical results indicate that fidelities are ultimately bottlenecked by spin-valley physics, which can be suppressed through the use of quantum optimal control, and we demonstrate that, across different potential regimes and competing physical models, shuttling based single-qubit gates retain significant advantage over existing alternatives.
Quantum physics describes the universe on a microscopic scale. Even though this scale is not accessible without complex experimental setups, quantum effects are respon- sible for the properties of matter and in some instances we have learned to exploit them technologically. A modern computer constituted of transistors passively utilizes the quantum nature of charge carriers in the band structure of semiconductors to encode and process information. Although such a classical computer is a formidable tool already, what could be achieved with active control over the quantum states in the computer is an intriguing question. This is the idea of the quantum computer, which offers an entirely new paradigm of computing by encoding information in quantum binary digits (qubits). Indeed, for several applications it has been shown that a quantum computer is superior to its classical counterpart, even though its realization remains elusive up to date. One candidate to host qubits are gate-defined semiconductor quantum dots, confin- ing single or few charge carriers with spin. The spin of a single confined electron is a quantum two-level system which can be manipulated and measured, allowing the storage and processing of quantum information. This thesis can be viewed as part of the endeavor to give birth to quantum computers based on semiconductor spin qubits. It primarily focuses on the challenge to enable scalable architectures of well-characterized qubits. In the first part, spin shuttling is investigated. This denotes the coherent transport of a single spin between spatially separate nodes of a quantum processor, driven by a time-dependent electric potential. The object of study is a minimal version of a bucket- brigade-like spin shuttling between two quantum dots. The probability of maintaining the spin state is identified as figure of merit and the effect of spin-orbit interaction and the Zeeman effect in an inhomogeneous magnetic field is explored with analytical and numerical methods. Special attention is paid to the repercussions of near-degenerate valleys. The second part of the thesis addresses the challenge to probe the microscopic properties of a quantum dot array, which is a crucial first step before any quantum operation can be performed. The transmission of a microwave resonator coupled to a triple quantum dot occupied by two electrons is investigated, and a scheme to infer the exchange interaction between electrons in adjacent quantum dots is proposed. By means of analytical derivations it is shown that the transmission profile of the resonator directly reveals the value of the exchange coupling strength between two electrons. This holds even if magnetic gradients or a valley splitting comparable to the inter-dot tunnel coupling are included. Subsequently, quantum transport measurements in the Pauli blockade regime are modelled in the presence of a microwave resonator, bringing together two powerful techniques to probe quantum dots. Based on generalized input-output theory, a theoretical framework is derived to investigate how a double quantum dot in a transport setup interacts with a coupled microwave resonator while the current through the double qauntum dot is rectified by Pauli blockade. It is shown that the output field of the resonator can be used to infer the leakage current and thus obtain insight into the blockade mechanisms and to estimate a large number of parameters of the quantum dots. Furthermore, the back-action of the resonator photons on the steady state leakage current is described and quantified. In the context of Pauli blockade, the spin and valley physics of bilayer graphene quantum dots in the few-electron regime is touched upon, describing a situation where spin blockade is observed despite the presence of the valleys. In the final part of the thesis, the attention is shifted towards the readout of the spin qubits. A new paradigm of dispersive readout is devised, which is performed while the qubit dephases, implementing a measurement in the x-basis. Laplace transforming the time dependent cavity response allows a separation of contributions from multiple qubits coupled to the same resonator. Thus, they can be read out simultaneously in a single shot. Modelling silicon spin qubits, as an example, results in in a readout time that compares favourably to conventional dispersive readout with comparable fidelity, even for a single qubit. With an auxiliary qubit the readout scheme can be extended to a quantum non-demolition measurement.