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IEEE Transactions on Applied Superconductivity

Single Source SFQ Multiclock Generator Using Resistor–JTL Branches

Tejumadejesu Oluwadamilare, Shay Hacohen-Gourgy, Eby G. Friedman

Published Nov 7, 2025• 0 citations
Publisher

Abstract

Systems requiring multiple clock frequencies are becoming more common in digital superconductive electronics. In rapid single flux quantum (RSFQ) circuits, precise frequencies are applied to different clock domains. A diverse variety of SFQ clock generators have been employed to produce a single frequency. A clock generator that uses a single voltage source to deliver multiple frequencies is presented here. The operating principle, performance, area, and power of the proposed SFQ multi-clock generator are described. Previously published clock generators are limited to a fixed frequency or varied by changing the bias DC voltage—a parameter not typically changedin situ. In the proposed approach, the clock frequency is tunable by the SFQ logic circuit. In addition, a globally asynchronous locally synchronous system is presented to exemplify the practical application of the proposed multi-clock generator

DOI
10.1109/tasc.2025.3630889

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Systems requiring multiple clock frequencies are becoming more common in digital superconductive electronics. In rapid single flux quantum (RSFQ) circuits, precise frequencies are applied to different clock domains. A diverse variety of SFQ clock generators have been employed to produce a single frequency. A clock generator that uses a single voltage source to deliver multiple frequencies is presented here. The operating principle, performance, area, and power of the proposed SFQ multi-clock generator are described. Previously published clock generators are limited to a fixed frequency or varied by changing the bias DC voltage—a parameter not typically changedin situ. In the proposed approach, the clock frequency is tunable by the SFQ logic circuit. In addition, a globally asynchronous locally synchronous system is presented to exemplify the practical application of the proposed multi-clock generator
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
Abstract We demonstrate the frequency synchronization of multiple single-flux quantum (SFQ) oscillators with different oscillation frequencies. To synchronize these SFQ oscillators, a common constant bias current is supplied to the SFQ oscillators without any bias resistors. When an SFQ oscillator oscillates at a frequency of f, the average voltage across the Josephson junction comprising the SFQ oscillator is f Φ 0 , where Φ 0 is the flux quantum in the superconductor. The bias currents supplied to the SFQ oscillators are redistributed to eliminate the average voltage difference output from the SFQ oscillators. As a result, the oscillation frequencies of all the SFQ oscillators are synchronized. Simulation results indicate that SFQ oscillators with an oscillation frequency difference of more than 50 GHz can be synchronized. We experimentally demonstrate the frequency synchronization of two SFQ oscillators composed of circular Josephson transmission lines. Frequency synchronization is expected to contribute toward the development of a low-power stable clock source stabilizing SFQ circuit operation.
This paper presents a basic circuit concept for pulse-driven asynchronous circuits using superconducting rapid single-flux-quantum (RSFQ) logic gates. Today's computer systems perform using a synchronous clock distributed over the whole system. The distribution of the clock signal becomes more difficult as the clock frequency increases because the wavelength of the clock signal becomes shorter than the system size. One way to solve this problem is to use asynchronous circuits in which all circuits perform their functions only under the law of cause and effect. We propose an implementation of the basic asynchronous circuit performing OR/AND logic operations between SFQ pulses. The operations are confirmed by SPICE simulation. We will show a design method for combinational circuits using the proposed basic circuits.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ liming schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic-gales and a asynchronous full adder was implemented and tested.
Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.