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Superconductor Science and Technology

Frequency synchronization of single flux quantum oscillators

Yuki Yamanashi, Ryo Kinoshita, Nobuyuki Yoshikawa

Published Aug 13, 2021• 10 citations
Publisher

Abstract

Abstract We demonstrate the frequency synchronization of multiple single-flux quantum (SFQ) oscillators with different oscillation frequencies. To synchronize these SFQ oscillators, a common constant bias current is supplied to the SFQ oscillators without any bias resistors. When an SFQ oscillator oscillates at a frequency of f, the average voltage across the Josephson junction comprising the SFQ oscillator is f Φ 0 , where Φ 0 is the flux quantum in the superconductor. The bias currents supplied to the SFQ oscillators are redistributed to eliminate the average voltage difference output from the SFQ oscillators. As a result, the oscillation frequencies of all the SFQ oscillators are synchronized. Simulation results indicate that SFQ oscillators with an oscillation frequency difference of more than 50 GHz can be synchronized. We experimentally demonstrate the frequency synchronization of two SFQ oscillators composed of circular Josephson transmission lines. Frequency synchronization is expected to contribute toward the development of a low-power stable clock source stabilizing SFQ circuit operation.

DOI
10.1088/1361-6668/ac1d96

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Abstract We demonstrate the frequency synchronization of multiple single-flux quantum (SFQ) oscillators with different oscillation frequencies. To synchronize these SFQ oscillators, a common constant bias current is supplied to the SFQ oscillators without any bias resistors. When an SFQ oscillator oscillates at a frequency of f, the average voltage across the Josephson junction comprising the SFQ oscillator is f Φ 0 , where Φ 0 is the flux quantum in the superconductor. The bias currents supplied to the SFQ oscillators are redistributed to eliminate the average voltage difference output from the SFQ oscillators. As a result, the oscillation frequencies of all the SFQ oscillators are synchronized. Simulation results indicate that SFQ oscillators with an oscillation frequency difference of more than 50 GHz can be synchronized. We experimentally demonstrate the frequency synchronization of two SFQ oscillators composed of circular Josephson transmission lines. Frequency synchronization is expected to contribute toward the development of a low-power stable clock source stabilizing SFQ circuit operation.
A Josephson single-flux-quantum voltage/frequency multiplier circuit is proposed as the basic building block for a new generation of voltage standards. The circuit uses magnetic coupling to synchronize a series array of independent junction oscillators to the flux flow in a Josephson transmission line. A cascade of these circuits can multiply an arbitrarily low input frequency up to the frequency limit of the circuit ( approximately=250 GHz) and then add the voltages across approximately 30000 oscillators to generate precise voltages up to 10 V. Because the oscillators can be switched on and off with a bias current, the output voltage is rapidly programmable. A complete design for a voltage standard programmable in 1.2- mu V increments to a maximum of 10 V is proposed. Using existing fabrication technology, the circuit would cover a substrate area of about 1 cm/sup 2/ and use 67210 junctions.>
Systems requiring multiple clock frequencies are becoming more common in digital superconductive electronics. In rapid single flux quantum (RSFQ) circuits, precise frequencies are applied to different clock domains. A diverse variety of SFQ clock generators have been employed to produce a single frequency. A clock generator that uses a single voltage source to deliver multiple frequencies is presented here. The operating principle, performance, area, and power of the proposed SFQ multi-clock generator are described. Previously published clock generators are limited to a fixed frequency or varied by changing the bias DC voltage—a parameter not typically changedin situ. In the proposed approach, the clock frequency is tunable by the SFQ logic circuit. In addition, a globally asynchronous locally synchronous system is presented to exemplify the practical application of the proposed multi-clock generator
We report low-power single-flux-quantum (SFQ) circuits fabricated with a lowered critical current density process and low-voltage design. We selected 250 A/cm2^{2}2to obtain 2–10 μA Josephson junctions (JJs) easily using conventional facilities. Our numerical simulation shows that the expected operating frequency is 10 GHz and that we can reduce the bias voltage to 0.1–0.5 mV; power consumption can be reduced to around 1 nW per JJ. We newly developed a fabrication process featuring four planarized Nb layers and a Pd resistor layer. We obtained the correct operation of several basic SFQ circuit elements designed with the lowered critical currents to 1/2 of the conventional circuits at 4.2 K. We also evaluated the Josephson junction critical currents, specific capacitance, resistance, and inductance at 3 K and 300 mK. We observed an increase of 7% in the critical currents at 300 mK, while the other parameters were unchanged. We demonstrated a 0.5-mV Josephson transmission line where we lowered the critical currents to 1/10. We expect such low-power SFQ circuits to operate at 20 mK, providing classical, general-purpose digital processing near quantum bits.
On-chip, high-frequency clock sources are essential for the future development of superconductor digital circuits and systems. We have developed clock sources for rapid single flux quantum (RSFQ) digital circuits using high-quality long Josephson junction (LJJ) resonant oscillators that offer extremely low jitter. To meet the requirement for time-interleaved clock signals of complementary phase, two-phase 30 and 50 GHz clock sources using LJJ's have been developed with both linear and annular geometry. Unperturbed by reflections from boundaries and collisions among the fluxons (flux quanta), the annular LJJ oscillator has demonstrated superior stability and higher quality factor (>10/sup 6/) than the linear LJJ oscillator. The LJJ oscillator with linear geometry is easier to interface with RSFQ circuitry since it has well-defined boundaries at either end, facilitating a two-phase clock source. On the other hand, multiple clock phases may be derived from an annular LJJ oscillator by connecting interface circuitry at various points around the circular junction, if the interface circuitry does not interfere with the fluxon(s) in the annular junction. Experimental results for two-phase RSFQ clock sources based on linear and annular LJJ oscillators are presented.
HYPRES has developed a monolithic on-chip phase-locked loop (PLL) for the stabilizing and locking of the high-frequency output of an single flux quantum (SFQ) clock source, using rapid single flux quantum (RSFQ) logic family elements for phase detection and frequency detection. This PLL was successfully fabricated and operated as a 50 GHz clock phase-locked to a MHz frequency external source. We were able to employ a feedback loop filter to correct the voltage bias on the SFQ clock and compensate for the frequency fluctuations created by voltage noise in the bias and shunt resistors. This effort resulted is a stable SFQ clock which is tunable and phase-locked to an external signal of lower frequency, and which does not increase the heat load of a circuit. Moreover, in addition to high speed synchronized clock sources, this PLL can now be used to implement new and useful devices, such as phase demodulators and clock recovery circuits.
Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~106years.