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Quantum Algorithm Emulation Using FPGAs

Samuel Petruescu

Published Jul 24, 2025• 0 citations
Publisher

Abstract

Field Programmable Gate Arrays (FPGAs) have been used in most of the physics sub-fields for various unique purposes. This includes particle physics, quantum optics, and, more recently, quantum computing. FPGAs boast many benefits over previous experimental and computational setups. They are versatile, easy to program, and cost-effective, leading to an understandable desire to incorporate them into the new field of quantum computing. While FPGAs have been used to help control the readout and control of physical qubits, they can also be a good tool for improving algorithm simulations, which is the focus of this paper. Different algorithms have different computational limits because of the varying operations and circuit depth levels. Due to the ease of incorporating parallel processes and the ability to optimize FPGAs on a deeper level, we can speed up computationally expensive operations, increasing the size of the quantum circuits we can simulate. This paper aims to provide an educational walkthrough for quantum computing physicists interested in taking advantage of FPGAs in their research. Our findings indicate that an inexpensive FPGA with a clock rate of 100MHz can perform simple, unoptimized matrix operations on the order of 107 ns faster than a CPU using optimized Python libraries. This can be further improved upon using more expensive hardware and optimized designs. This will provide many researchers and students with the tools needed to study quantum algorithms without the need for costly hardware.

DOI
10.31979/etd.28de-9p2u

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Field Programmable Gate Arrays (FPGAs) have been used in most of the physics sub-fields for various unique purposes. This includes particle physics, quantum optics, and, more recently, quantum computing. FPGAs boast many benefits over previous experimental and computational setups. They are versatile, easy to program, and cost-effective, leading to an understandable desire to incorporate them into the new field of quantum computing. While FPGAs have been used to help control the readout and control of physical qubits, they can also be a good tool for improving algorithm simulations, which is the focus of this paper. Different algorithms have different computational limits because of the varying operations and circuit depth levels. Due to the ease of incorporating parallel processes and the ability to optimize FPGAs on a deeper level, we can speed up computationally expensive operations, increasing the size of the quantum circuits we can simulate. This paper aims to provide an educational walkthrough for quantum computing physicists interested in taking advantage of FPGAs in their research. Our findings indicate that an inexpensive FPGA with a clock rate of 100MHz can perform simple, unoptimized matrix operations on the order of 107 ns faster than a CPU using optimized Python libraries. This can be further improved upon using more expensive hardware and optimized designs. This will provide many researchers and students with the tools needed to study quantum algorithms without the need for costly hardware.
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Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.
In the past decades, field-programmable gate arrays (FPGAs) have demonstrated an interesting physical platform to facilitate quantum information processing, particularly in the emergence of domain-specific hardware accelerators for quantum computing emulation and quantum key distillation. While conventional general-purpose hardware platforms have been used for quantum information processing, FPGAs promise deep pipeline parallelism, adaptable interface, and trivial support for custom-precision operation. Therefore, the time is ripe for describing recent development of quantum computing emulators and quantum key distillation accelerators on FPGAs. In this article, we provide a comprehensive review of the state-of-the-art in this active field, with a balance between theoretical, implementational, and technological results. Challenges and promising research opportunities are also discussed.
As current trend of miniaturization in computing technology continues, modern computing devices would start to exhibit the behaviour of nanoscopic quantum objects. Quantum computing, which is based on the principles of quantum mechanics, becomes a promising candidate for future generation computing system. However, modelling quantum computing systems on existing classical computing platforms before the realization of viable large-scale quantum computer remains a major challenge. The exploration on the modelling of quantum computing systems on field programmable gate array (FPGA) platform, which offers the potential of massive parallelism and allows computational optimization at register-transfer level, is crucial. Due to the exponential growth of resource utilization with the increase in the number of quantum bits (qubit), existing works on modelling of quantum systems on FPGA platform are restricted to simple case studies using small qubit sizes. This work explores the modelling of quantum computing for emulation on FPGA platform based on two types of data structure: (a) state vector model and (b) Heisenberg model. For the conventional state vector modelling approach, an efficient datapath design that is based on serial-parallel hardware architecture, which allows resource sharing between unitary transformations, is proposed. Heisenberg model has been proven to be efficient in modelling stabilizer circuits, which are critical in error correction operations. In the effort to include the consideration of vital quantum error correction in practical quantum systems, a novel FPGA emulation framework that is based on the Heisenberg model is proposed. Effective algorithms for accurate global phase maintenance are proposed to facilitate the modelling of quantum systems based on the Heisenberg representation. The feasibility of the proposed state vector and Heisenberg emulation models are demonstrated based on a number of case studies with different characteristics, which include quantum Fourier transform, Grover’s search algorithm, and stabilizer circuits. Based on the state vector approach, this work has demonstrated the advantage of FPGA emulation over software simulation where hardware emulation of 7-qubit Grover’s search is about 3 × 104 times faster than the software simulation performed on Intel Core i7-4790 processor running at 3.6GHz clock rate. In contrast to the 8-qubit implementation based on the state vector model, the proposed FPGA emulation framework based on the Heisenberg model has successfully modelled 120-qubit stabilizer circuits on the Altera Stratix IV FPGA. In summary, the proposed work in this thesis contributes to the formulation of a proof-of-concept of efficient FPGA emulation framework based on the state vector and Heisenberg models.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.