Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

FPGA quantum computing emulator using high level design tools

Agustin Silva, Omar Gustavo Zabaleta

Published Aug 1, 2017• 22 citations
Publisher

Abstract

Although, there have been considerable advances in quantum technology, a great scale quantum computer will not be available until about a few years. In the meantime, it requires quantum emulators which allow to study the existing quantum algorithms and the design of new ones. We propose a flexible method to emulate quantum circuits which reduces design and processing time. In this context, we propose a design framework that takes advantage of field-programmable gate array (FPGA) parallel processing technology in combination with high-level programming tools provided by Vivado. In order to show the design method working Quantum Fourier Transform (QFT) is implemented. Every step of the design is described and circuit performance is studied for different cases of input vector data sizes.

DOI
10.23919/sase-case.2017.8115369

Related papers

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Y. H. Lee, Mohamed Khalil-Hani, Muhammad Nadzir Marsono

Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

International Journal of Reconfigurable Computing•Jan 1, 2016•38 citations

FPGA-based quantum circuit emulation: A case study on Quantum Fourier transform

Y. H. Lee, Mohamed Khalil-Hani, Muhammad Nadzir Marsono

Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.

International Symposium on Integrated Circuits•Dec 1, 2014•6 citations

An Accurate FPGA-Based Hardware Emulation on Quantum Fourier Transform

Mohamed Khalil-Hani, Y. H. Lee, Muhammad Nadzir Marsono

Powerful parallelism is among the leading attractions to- wards quantum computing research. Before large-scale quantum computers become viable, the use of field- programmable gate array (FPGA) technology which can mimic the behavior of quantum parallelism is vital. In this paper, a methodology to perform mapping of quan- tum algorithms for efficient quantum hardware emulations is proposed. The case study to demonstrate the proposed methodology is the emulation of quantum Fourier trans- form. With the design considerations on the superposi- tion and entangled input state as well as the choice of ef- ficient hardware architecture, the proposed work provides a guideline for conducting accurate FPGA-based quantum hardware emulations for practical quantum applications.

•Jan 1, 2015•17 citations

Quantum Algorithm Emulation Using FPGAs

Samuel Petruescu

Field Programmable Gate Arrays (FPGAs) have been used in most of the physics sub-fields for various unique purposes. This includes particle physics, quantum optics, and, more recently, quantum computing. FPGAs boast many benefits over previous experimental and computational setups. They are versatile, easy to program, and cost-effective, leading to an understandable desire to incorporate them into the new field of quantum computing. While FPGAs have been used to help control the readout and control of physical qubits, they can also be a good tool for improving algorithm simulations, which is the focus of this paper. Different algorithms have different computational limits because of the varying operations and circuit depth levels. Due to the ease of incorporating parallel processes and the ability to optimize FPGAs on a deeper level, we can speed up computationally expensive operations, increasing the size of the quantum circuits we can simulate. This paper aims to provide an educational walkthrough for quantum computing physicists interested in taking advantage of FPGAs in their research. Our findings indicate that an inexpensive FPGA with a clock rate of 100MHz can perform simple, unoptimized matrix operations on the order of 107 ns faster than a CPU using optimized Python libraries. This can be further improved upon using more expensive hardware and optimized designs. This will provide many researchers and students with the tools needed to study quantum algorithms without the need for costly hardware.

•Jul 24, 2025•0 citations

A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory

Hasitha Muthumala Waidyasooriya, Hiroki Oshiyama, Yuya Kurebayashi +2 more

Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not have the capability to correct errors caused by environmental noise, so that it is difficult to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in digital computers is essential. However, emulation of large quantum circuits requires enormous amount of computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up to 30 qubits using two FPGAs. According to the measured results, we have achieved 23.6 ~ 24.5 times speed-up compared to a fully optimized 24-core CPU emulator.

IEEE Access•Jan 1, 2022•16 citations

Efficient FPGA Emulation of Quantum Fourier Transform

Yu Qian, Mingyu Wang, Jialin Chen +2 more

Quantum computation shows its great advantage on exponential speed-up for some complex algorithms. Compared to software simulation with sequential execution, hardware emulation based on Field Programmable Gate Array (FPGA) can help to realize the intrinsic quantum parallelism. Quantum Fourier Transform (QFT) is the core of several quantum algorithms like Shor's algorithm. This paper proposes a recursive decomposition of QFT-n, which can be emulated with a pipeline architecture based on Intel Stratix IV FPGA device. Although QFT-8 is much more complex than QFT-5, experimental results show that our QFT-8 architecture can reduces 91% DSP blocks and 76% combinational ALUTs at the cost of 11x registers compared with QFT-5 in [4] on average.

China Semiconductor Technology International Conference (CSTIC)•Mar 1, 2019•6 citations
Although, there have been considerable advances in quantum technology, a great scale quantum computer will not be available until about a few years. In the meantime, it requires quantum emulators which allow to study the existing quantum algorithms and the design of new ones. We propose a flexible method to emulate quantum circuits which reduces design and processing time. In this context, we propose a design framework that takes advantage of field-programmable gate array (FPGA) parallel processing technology in combination with high-level programming tools provided by Vivado. In order to show the design method working Quantum Fourier Transform (QFT) is implemented. Every step of the design is described and circuit performance is studied for different cases of input vector data sizes.
Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.
Powerful parallelism is among the leading attractions to- wards quantum computing research. Before large-scale quantum computers become viable, the use of field- programmable gate array (FPGA) technology which can mimic the behavior of quantum parallelism is vital. In this paper, a methodology to perform mapping of quan- tum algorithms for efficient quantum hardware emulations is proposed. The case study to demonstrate the proposed methodology is the emulation of quantum Fourier trans- form. With the design considerations on the superposi- tion and entangled input state as well as the choice of ef- ficient hardware architecture, the proposed work provides a guideline for conducting accurate FPGA-based quantum hardware emulations for practical quantum applications.
Field Programmable Gate Arrays (FPGAs) have been used in most of the physics sub-fields for various unique purposes. This includes particle physics, quantum optics, and, more recently, quantum computing. FPGAs boast many benefits over previous experimental and computational setups. They are versatile, easy to program, and cost-effective, leading to an understandable desire to incorporate them into the new field of quantum computing. While FPGAs have been used to help control the readout and control of physical qubits, they can also be a good tool for improving algorithm simulations, which is the focus of this paper. Different algorithms have different computational limits because of the varying operations and circuit depth levels. Due to the ease of incorporating parallel processes and the ability to optimize FPGAs on a deeper level, we can speed up computationally expensive operations, increasing the size of the quantum circuits we can simulate. This paper aims to provide an educational walkthrough for quantum computing physicists interested in taking advantage of FPGAs in their research. Our findings indicate that an inexpensive FPGA with a clock rate of 100MHz can perform simple, unoptimized matrix operations on the order of 107 ns faster than a CPU using optimized Python libraries. This can be further improved upon using more expensive hardware and optimized designs. This will provide many researchers and students with the tools needed to study quantum algorithms without the need for costly hardware.
Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not have the capability to correct errors caused by environmental noise, so that it is difficult to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in digital computers is essential. However, emulation of large quantum circuits requires enormous amount of computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up to 30 qubits using two FPGAs. According to the measured results, we have achieved 23.6 ~ 24.5 times speed-up compared to a fully optimized 24-core CPU emulator.
Quantum computation shows its great advantage on exponential speed-up for some complex algorithms. Compared to software simulation with sequential execution, hardware emulation based on Field Programmable Gate Array (FPGA) can help to realize the intrinsic quantum parallelism. Quantum Fourier Transform (QFT) is the core of several quantum algorithms like Shor's algorithm. This paper proposes a recursive decomposition of QFT-n, which can be emulated with a pipeline architecture based on Intel Stratix IV FPGA device. Although QFT-8 is much more complex than QFT-5, experimental results show that our QFT-8 architecture can reduces 91% DSP blocks and 76% combinational ALUTs at the cost of 11x registers compared with QFT-5 in [4] on average.