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International Conference on Applied Electronics

The hardware implementation of a quantum computation system emulator

Laurenţiu Mihai Ionescu, Alin Gheorghita Mazare, Constantin Anton, Catalin Stoian

Published Sep 1, 2014• 2 citations
Publisher

Abstract

The quantum computing represents a new field, which is still being researched, that may have numerous applications in the computer arithmetic, in the encryption - decryption systems, rapid search algorithms and physical systems' emulations. The hardware device that can make this type of calculations is still expensive nowadays and the number of the manufacturers is reduced. On the other hand, the simulation of a quantum computer using the devices currently available on the market - like the FPGA digital circuits - helps in getting an overview of the possibilities that the quantum calculations can provide and it can also be used when simulating physical processes in general. The aim of this article is to present our own solution of an emulator for the quantum calculations using the digital modules implemented in FPGA.

DOI
10.1109/ae.2014.7011682

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Quantum computing offers immense speedup in performing tasks such as data encryption and searching. The quantum algorithms can be modeled using classical computing devices, however classical computer simulations cannot deal efficiently with the parallelism present in quantum algorithms. The quantum circuit model for quantum algorithms is sufficient to describe the known quantum algorithms. Using analogies between quantum and digital circuits, we design the emulator of quantum algorithms in FPGAs that allows efficient experimentation with new quantum algorithms. This paper concentrates on new techniques for modeling quantum circuits, including the entanglement and probabilistic computing realization, as well as the critical issues in the required precision of computing.
It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.
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The rapidly developing field of quantum computing and the ongoing lack of widely available quantum computers create the need for scientists to build their simulators. However, mathematical simulation of such circuits usually ignores many aspects and problems found in real quantum systems. In this article, the authors describe a quantum bit emulator based on FPGA integrated circuits. In this case, FPGA technology provides real-time massive parallelism of the modeled physical phenomena. The modeled QUBIT is represented using a Bloch sphere. Its quantum state is set and modified only by precise pulses of an electrical signal, and with the help of similar pulses, it manifests its current state in real time. The constructed QUBIT was additionally equipped with decoherence mechanisms and with circuits that intentionally respond to internal and external noises that distort its current quantum state. This article presents and discusses how such a physically built emulator works.
Quantum computer emulators implemented on FPGA are generally designed to illustrate possible applications in which these concepts can be used - as a method of functional testing of possible applications involving quantum computing. In this paper we try to present another possible use of a quantum computation emulator, proposed by the authors, for the synthesis of circuits in FPGA with superior performance to conventional or parallel design methods. The paper presents a synthesis solution of parallel structures based on concepts from quantum computation emulated on FPGA. As will be seen in the paper, using the solution improves the computation time compared to the conventional method and reduces the number of resources allocated compared to the parallel solution. So, the solution which we propose is somewhere between conventional sequential logic circuit design methods - it has a shorter response time than these and parallel circuit design methods - it provides a smaller number of resources than these. In order to show the advantages of the proposed solution, we presented the implementation of a circuit for determining the parity of a binary function. The solution was implemented using the conventional solution, the parallel solution and the proposed solution using quantum computing concepts. It will show the performance of the proposed solution compared to the other design models.