Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Japanese Journal of Applied Physics

16-Qubit Quantum-Computing Emulation Based on High-Speed Hardware Architecture

Minoru Fujishima, Kosuke Saito, Koichiro Hoh

Published Apr 30, 2003• 19 citations
Publisher

Abstract

A 16-qubit quantum-computing emulator executing quantum algorithms at high speed is proposed. By limiting the command of the quantum computing emulator to the minimum function required with the quantum algorithm, probability amplitudes are expressed with one bit and the functions of many qubits are integrated on a field programmable gate array (FPGA). As a result of implementing the emulator in the FPGA, it is found that the emulator has a 250 times higher-speed as compared with a software simulation by a general-purpose processor.

DOI
10.1143/jjap.42.2182

Related papers

High-speed processor for quantum-computing emulation and its applications

Minoru Fujishima, Keiji Saito, Masafumi Onouchi +1 more

A high-speed and large-scale processor dedicated to quantum computing is proposed, which has the minimum operation function needed for execution of a quantum algorithm. In this processor, the probability amplitudes determined by the states of the quantum bits in the quantum computer are described using only one bit, and we named it a logic quantum processor. It is found that for this processor an execution speed 275 times higher than that of a software simulation is obtained when the processor executing the quantum algorithm for 16 qubit has been implemented in a FPGA. As an example application, it is shown that the processor can solve the satisfiability problem and that it can also simulate the decoherence in the quantum computer at high speed.

IEEE International Symposium on Circuits and Systems proceedings•Nov 4, 2003•10 citations

FPGA-based high-speed emulator of quantum computing

Minoru Fujishima

Quantum computers are believed to perform high-speed calculations, compared with conventional computers. However, the quantum computer has inherent issues. Firstly, it solves NP (non-deterministic polynomial) problems at a high speed only when a periodic function can be used in the process of calculation. Secondly, it is extremely difficult to increase the problem scale to be solved, which is determined by the number of quantum bits. To overcome the restrictions stemming from the quantum algorithm, we are studying the emulation by a FPGA (field programmable gate array). In this paper, first, it is explained why a periodic function is required for the algorithm of a quantum computer. Then, it is shown that the hardware emulator can solve NP problems at a high speed without using a periodic function.

International Conference on Field-Programmable Technology (FPT)•Jun 30, 2004•25 citations

A Scalable High-Precision and High-Throughput Architecture for Emulation of Quantum Algorithms

Naveed Mahmud, Esam El‐Araby

Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.

IEEE International System-on-Chip Conference (SOCC)•Sep 1, 2018•12 citations

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Y. H. Lee, Mohamed Khalil-Hani, Muhammad Nadzir Marsono

Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

International Journal of Reconfigurable Computing•Jan 1, 2016•38 citations

FPGA-Based Circuit Model Emulation of Quantum Algorithms

Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani +1 more

It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.

IEEE Computer Society Annual Symposium on VLSI•Jan 1, 2008•43 citations

Improving Emulation of Quantum Algorithms using Space-Efficient Hardware Architectures

Naveed Mahmud, Esam El‐Araby

With rapid advancement in quantum computing technology, continuous efforts are being directed to simulation and emulation of quantum algorithms on classical platforms. A well-known limitation to classical emulation of quantum circuits is scalability. Existing hardware emulators implement gate-based circuit models of quantum circuits that result in heavy resource utilization and degrade the scalability of the system. Also, current quantum emulation hardware use fixedpoint arithmetic, which has an adverse effect on accuracy when the system is scaled up. In this work, we employ a complexmultiply-and-accumulate (CMAC) and lookup-based emulation approach that greatly reduces resource utilization and improves system scalability in terms of number of emulated qubits. We demonstrate emulation of up to 16 fully-entangled qubits which is highest among existing work. We design fully-pipelined, highthroughput hardware architectures that use floating-point precision for higher accuracy. Experimental evaluation and analysis of the architectures in terms of speed and area is also provided. The emulator is prototyped on a high-performance reconfigurable computing (HPRC) system and our results demonstrate quantitative improvement over existing Field-Programmable-Gate-Array (FPGA)-based hardware emulators.

IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)•Jul 1, 2019•2 citations
A 16-qubit quantum-computing emulator executing quantum algorithms at high speed is proposed. By limiting the command of the quantum computing emulator to the minimum function required with the quantum algorithm, probability amplitudes are expressed with one bit and the functions of many qubits are integrated on a field programmable gate array (FPGA). As a result of implementing the emulator in the FPGA, it is found that the emulator has a 250 times higher-speed as compared with a software simulation by a general-purpose processor.
A high-speed and large-scale processor dedicated to quantum computing is proposed, which has the minimum operation function needed for execution of a quantum algorithm. In this processor, the probability amplitudes determined by the states of the quantum bits in the quantum computer are described using only one bit, and we named it a logic quantum processor. It is found that for this processor an execution speed 275 times higher than that of a software simulation is obtained when the processor executing the quantum algorithm for 16 qubit has been implemented in a FPGA. As an example application, it is shown that the processor can solve the satisfiability problem and that it can also simulate the decoherence in the quantum computer at high speed.
Quantum computers are believed to perform high-speed calculations, compared with conventional computers. However, the quantum computer has inherent issues. Firstly, it solves NP (non-deterministic polynomial) problems at a high speed only when a periodic function can be used in the process of calculation. Secondly, it is extremely difficult to increase the problem scale to be solved, which is determined by the number of quantum bits. To overcome the restrictions stemming from the quantum algorithm, we are studying the emulation by a FPGA (field programmable gate array). In this paper, first, it is explained why a periodic function is required for the algorithm of a quantum computer. Then, it is shown that the hardware emulator can solve NP problems at a high speed without using a periodic function.
Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.
Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.
It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.
With rapid advancement in quantum computing technology, continuous efforts are being directed to simulation and emulation of quantum algorithms on classical platforms. A well-known limitation to classical emulation of quantum circuits is scalability. Existing hardware emulators implement gate-based circuit models of quantum circuits that result in heavy resource utilization and degrade the scalability of the system. Also, current quantum emulation hardware use fixedpoint arithmetic, which has an adverse effect on accuracy when the system is scaled up. In this work, we employ a complexmultiply-and-accumulate (CMAC) and lookup-based emulation approach that greatly reduces resource utilization and improves system scalability in terms of number of emulated qubits. We demonstrate emulation of up to 16 fully-entangled qubits which is highest among existing work. We design fully-pipelined, highthroughput hardware architectures that use floating-point precision for higher accuracy. Experimental evaluation and analysis of the architectures in terms of speed and area is also provided. The emulator is prototyped on a high-performance reconfigurable computing (HPRC) system and our results demonstrate quantitative improvement over existing Field-Programmable-Gate-Array (FPGA)-based hardware emulators.