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IEEE International Symposium on Circuits and Systems proceedings

High-speed processor for quantum-computing emulation and its applications

Minoru Fujishima, Keiji Saito, Masafumi Onouchi, H. Hoh

Published Nov 4, 2003• 10 citations
Publisher

Abstract

A high-speed and large-scale processor dedicated to quantum computing is proposed, which has the minimum operation function needed for execution of a quantum algorithm. In this processor, the probability amplitudes determined by the states of the quantum bits in the quantum computer are described using only one bit, and we named it a logic quantum processor. It is found that for this processor an execution speed 275 times higher than that of a software simulation is obtained when the processor executing the quantum algorithm for 16 qubit has been implemented in a FPGA. As an example application, it is shown that the processor can solve the satisfiability problem and that it can also simulate the decoherence in the quantum computer at high speed.

DOI
10.1109/iscas.2003.1206362

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A high-speed and large-scale processor dedicated to quantum computing is proposed, which has the minimum operation function needed for execution of a quantum algorithm. In this processor, the probability amplitudes determined by the states of the quantum bits in the quantum computer are described using only one bit, and we named it a logic quantum processor. It is found that for this processor an execution speed 275 times higher than that of a software simulation is obtained when the processor executing the quantum algorithm for 16 qubit has been implemented in a FPGA. As an example application, it is shown that the processor can solve the satisfiability problem and that it can also simulate the decoherence in the quantum computer at high speed.
A 16-qubit quantum-computing emulator executing quantum algorithms at high speed is proposed. By limiting the command of the quantum computing emulator to the minimum function required with the quantum algorithm, probability amplitudes are expressed with one bit and the functions of many qubits are integrated on a field programmable gate array (FPGA). As a result of implementing the emulator in the FPGA, it is found that the emulator has a 250 times higher-speed as compared with a software simulation by a general-purpose processor.
A quantum computer is highly promising and widely studied since it enables a much higher calculation speed than current computers. Due to physical limitations, however, the current quantum computer can only solve much smaller scale problems than conventional computers. In order to process a large-scale problem at high speed, we have been studying a quantum computing emulator utilizing semiconductor memories. As a result, we have realized a dedicated processor that solves search problems, such as the satisfiability problem, at much higher speed than current computers. Consequently, without using "quantum process," the possibility of a quantum computer executing a large-scale problem is shown.
Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on a hardware, which can process a lot of operations in parallel. In this paper, we propose a processor architecture dedicated to simulating quantum algorithms. The proposed architecture is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implemented the processor on an FPGA. Experimental results show that the proposed processor has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.
Quantum computers are believed to perform high-speed calculations, compared with conventional computers. However, the quantum computer has inherent issues. Firstly, it solves NP (non-deterministic polynomial) problems at a high speed only when a periodic function can be used in the process of calculation. Secondly, it is extremely difficult to increase the problem scale to be solved, which is determined by the number of quantum bits. To overcome the restrictions stemming from the quantum algorithm, we are studying the emulation by a FPGA (field programmable gate array). In this paper, first, it is explained why a periodic function is required for the algorithm of a quantum computer. Then, it is shown that the hardware emulator can solve NP problems at a high speed without using a periodic function.
It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.
A high-speed solver of an inverse problem to a oneway function becomes important although the problems become complicated according to the change in social situation. However, a chip multiprocessor dedicated to the inverse problem to the one-way function is nonexistent although a single-chip processor consuming limited power is useful in realizing a high-speed solver. In this paper, we propose a new chip multiprocessor operating with a procedure similar to that of quantum computing. The chip multiprocessor is implemented on a field programmable gate array (FPGA), and the factorization of a 64-bit integer is demonstrated. As a result, the proposed processor reduces the calculation time by 35% compared with a general-purpose processor with 3.4GHz clock frequency. As a result, it is shown that the proposed processor solves inverse problems such as factorization and discrete logarithm problems at higher speed than a general-purpose processor consuming limited power.