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IFIP/IEEE International Conference on Very Large Scale Integration

A quantum algorithm processor architecture based on register reordering

Masaki Nakanishi, Miki Matsuyama, Yumi Yokoo

Published Oct 1, 2014• 0 citations
Publisher

Abstract

Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on a hardware, which can process a lot of operations in parallel. In this paper, we propose a processor architecture dedicated to simulating quantum algorithms. The proposed architecture is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implemented the processor on an FPGA. Experimental results show that the proposed processor has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.

DOI
10.1109/vlsi-soc.2014.7004175

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A high-speed and large-scale processor dedicated to quantum computing is proposed, which has the minimum operation function needed for execution of a quantum algorithm. In this processor, the probability amplitudes determined by the states of the quantum bits in the quantum computer are described using only one bit, and we named it a logic quantum processor. It is found that for this processor an execution speed 275 times higher than that of a software simulation is obtained when the processor executing the quantum algorithm for 16 qubit has been implemented in a FPGA. As an example application, it is shown that the processor can solve the satisfiability problem and that it can also simulate the decoherence in the quantum computer at high speed.
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Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.