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International Conference on Information and Communication Technology Convergence (ICTC)

Quantum Circuit Simulator based on FPGA

Yunpyo Hong, Seokhun Jeon, Sihyeong Park, Byung-Soo Kim

Published Oct 19, 2022• 13 citations
Publisher

Abstract

The quantum computer is emerging technology since it can resolve complex tasks such as factorization or search problem faster than classical computers. However, simulation of the quantum computer is difficult because computational load increases exponentially as the number of qubits used in the circuit is increased. This paper proposes a hardware architecture for quantum circuit simulation. To implement simulator smaller, our architecture operates based on a 1-input single gate regardless of the number of qubits used in the circuit In addition, our architecture helps to reduce simulation time by skipping calculation and data transfer. The proposed architecture is implemented on FPGA and the experimental results show that our architecture reduces 79.2% of the multiplication process when we simulate 20-qubit quantum Fourier transform with a small hardware size.

DOI
10.1109/ictc55196.2022.9952408

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The quantum computer is emerging technology since it can resolve complex tasks such as factorization or search problem faster than classical computers. However, simulation of the quantum computer is difficult because computational load increases exponentially as the number of qubits used in the circuit is increased. This paper proposes a hardware architecture for quantum circuit simulation. To implement simulator smaller, our architecture operates based on a 1-input single gate regardless of the number of qubits used in the circuit In addition, our architecture helps to reduce simulation time by skipping calculation and data transfer. The proposed architecture is implemented on FPGA and the experimental results show that our architecture reduces 79.2% of the multiplication process when we simulate 20-qubit quantum Fourier transform with a small hardware size.
The quantum computer has attracted much attention since it can reduce running time of many tasks such as factorization and search compared to classical computers. However, the actual quantum computer is difficult to get access, and the classical computer has a problem of calculation time and computation cost grows exponentially with increasing the number of qubits. In this paper, we address an efficient quantum circuit simulator including quantum circuit emulation hardware and its software framework using classical bit. Also, the proposed quantum circuit simulator operates the same as the conventional quantum software framework and shows a fast operation speed.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.
Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not have the capability to correct errors caused by environmental noise, so that it is difficult to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in digital computers is essential. However, emulation of large quantum circuits requires enormous amount of computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up to 30 qubits using two FPGAs. According to the measured results, we have achieved 23.6 ~ 24.5 times speed-up compared to a fully optimized 24-core CPU emulator.
Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.