Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with n qubits requires 2n+4 bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.
Abstract This paper presents a distributed quantum circuit statevector simulator thatpartitions the full 2n-amplitude state vector across four Xilinx Alveo U55C field-programmable gate arrays, each equipped with eight gigabytes of HBM2. Thearchitecture assigns two top-index qubits as partition bits so that card j ownsall amplitudes whose binary index has bits [n − 2, n − 1] equal to j, givingeach card a local statevector of 2n−2 complex double-precision amplitudes inter-leaved across eight HBM banks under a modulo-eight scheme. Gate executionis divided into three paths: local gates (acting on qubit indices below n − 2)are dispatched directly to the on-card HLS kernel; diagonal gates acting on par-tition qubits (controlled-phase, RZ , phase, CZ) are applied as a scalar phasemultiply without any cross-card data movement; and non-diagonal partition-qubit gates (Hadamard, CNOT) are handled by a three-barrier, double-bufferedshared-memory exchange followed by vectorised host arithmetic. This diagonal-gate local path eliminates cross-card traffic for every controlled-phase gate ina Quantum Fourier Transform, which would otherwise constitute the dominantcommunication bottleneck in a distributed QFT implementation.We validate the system across five quantum algorithm families on real hardware.The Quantum Fourier Transform achieves state fidelity F = 1.000000000000against an independent Qiskit statevector reference for all circuit widths fromn = 4 to n = 18 qubits, with wall-clock times ranging from 0.96 s at fourqubits to 19.1 s at eighteen qubits. Grover search circuits on up to ten qubitsachieve target-state probability exceeding 99.9% in all cases, with measuredfidelity F = 1.0 confirming exact computation on the FPGA hardware. GHZstate preparation, Bell pair generation, QFT–IQFT round-trips, and a nine-qubitShor algorithm component all pass at F = 1.000000000000. At twenty qubits, where each card holds 218 = 262,144 amplitudes consuming four megabytes ofHBM per card, the simulation completes correctly in under two minutes.Compared with the prior single-FPGA 30-qubit statevector engine, the distributed architecture extends the qubit ceiling to 28 qubits (4 GB total HBM)with exact complex128 precision, and removes the routing failure that prevented a sixteen-bank single-kernel design from placing on the XCVU55C. Comparedwith the Matrix Product State engine at 500 qubits, the statevector approachremains exact for arbitrary entanglement, at the cost of exponential memoryscaling rather than polynomial. The companion real-time quantum error correc-tion kernels and the native RTL statevector design together constitutea complete FPGA quantum computing stack, and the multi-FPGA distributedarchitecture presented here occupies the high-fidelity large-scale simulation tierof that stack.
A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).
Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to current quantum device limitations. Software simulators are time and memory-intensive, making hardware emulators an attractive alternative. This article introduces a digital architecture, designed to emulate quantum computing on low-tier Field-Programmable Gate Arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates quantum algorithm verification using a RISC-like structure and efficiently handling sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. The architecture is validated against the Qiskit state vector simulator, successfully emulating sixteen qubits on a Xilinx Kria KV260 SoM.
In recent years, there has been a growing interest in the development of quantum emulation. However, existing studies often struggle to achieve broad applicability, high performance, and efficient resource and memory utilization. To address these challenges, we provide HPQEA, a quantum emulator based on the state-vector emulation approach. HPQEA includes three main features: a high-performance computing core, an optimized controlled-NOT gate computation strategy, and effective utilization of high-bandwidth memory. Verification and evaluation on the Alveo U280 board show that HPQEA can emulate quantum circuits with up to 30 qubits while maintaining high fidelity and low mean square error. It outperforms comparable FPGA-based systems by producing faster execution, supporting a wider range of algorithms, and requiring low hardware resources. Furthermore, it exceeds the Nvidia A100 in normalized gate speed for systems with up to 20 qubits. These results demonstrate the scalability and efficiency of HPQEA as a platform for emulating quantum algorithms.
As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale quantum) era, quantum algorithm researchers cannot reliably test their algorithms on real quantum hardware, which is still too limited. Instead, quantum computing simulators on classical computing systems are used. In the quantum circuit model, quantum bits (qubits) are operated on by quantum gates. A quantum circuit is a sequence of such quantum gates operating on some number of qubits. A quantum gate applied to a qubit can be controlled by other qubits in the circuit. This applies the gate only to the states which satisfy the required control qubit state. We particularly target FPGAs as our main simulation platform, as these offer potential energy savings when compared to running simulations on CPUs/GPUs. In this work, we present a memory access pattern to optimise the number of iterations that need to be scheduled to execute a quantum gate such that only the iterations which access the required pairs (determined according to the control qubits imposed on the gate) are scheduled. We show that this approach results in a significant reduction in the time required to simulate a gate for each added control qubit. We also show that this approach benefits the simulation time on FPGAs more than CPUs and GPUs and allows to outperform both CPU and GPU platforms in terms of energy efficiency, which is the main factor for scalability of the simulations.