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IEEE Access

A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory

Hasitha Muthumala Waidyasooriya, Hiroki Oshiyama, Yuya Kurebayashi, Masanori Hariyama, Masayuki Ohzeki

Published Jan 1, 2022• 16 citations
Publisher

Abstract

Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not have the capability to correct errors caused by environmental noise, so that it is difficult to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in digital computers is essential. However, emulation of large quantum circuits requires enormous amount of computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up to 30 qubits using two FPGAs. According to the measured results, we have achieved 23.6 ~ 24.5 times speed-up compared to a fully optimized 24-core CPU emulator.

DOI
10.1109/access.2022.3183993

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Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not have the capability to correct errors caused by environmental noise, so that it is difficult to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in digital computers is essential. However, emulation of large quantum circuits requires enormous amount of computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up to 30 qubits using two FPGAs. According to the measured results, we have achieved 23.6 ~ 24.5 times speed-up compared to a fully optimized 24-core CPU emulator.
Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.
Quantum computation shows its great advantage on exponential speed-up for some complex algorithms. Compared to software simulation with sequential execution, hardware emulation based on Field Programmable Gate Array (FPGA) can help to realize the intrinsic quantum parallelism. Quantum Fourier Transform (QFT) is the core of several quantum algorithms like Shor's algorithm. This paper proposes a recursive decomposition of QFT-n, which can be emulated with a pipeline architecture based on Intel Stratix IV FPGA device. Although QFT-8 is much more complex than QFT-5, experimental results show that our QFT-8 architecture can reduces 91% DSP blocks and 76% combinational ALUTs at the cost of 11x registers compared with QFT-5 in [4] on average.
Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.
Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic) pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT) and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC) was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.
Although, there have been considerable advances in quantum technology, a great scale quantum computer will not be available until about a few years. In the meantime, it requires quantum emulators which allow to study the existing quantum algorithms and the design of new ones. We propose a flexible method to emulate quantum circuits which reduces design and processing time. In this context, we propose a design framework that takes advantage of field-programmable gate array (FPGA) parallel processing technology in combination with high-level programming tools provided by Vivado. In order to show the design method working Quantum Fourier Transform (QFT) is implemented. Every step of the design is described and circuit performance is studied for different cases of input vector data sizes.