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IEEE International Conference on Rebooting Computing (ICRC)

Towards Higher Scalability of Quantum Hardware Emulation Using Efficient Resource Scheduling

Naveed Mahmud, Esam El‐Araby

Published Nov 1, 2018• 9 citations
Publisher

Abstract

Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic) pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT) and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC) was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.

DOI
10.1109/icrc.2018.8638610

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Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic) pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT) and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC) was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.
Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.
With rapid advancement in quantum computing technology, continuous efforts are being directed to simulation and emulation of quantum algorithms on classical platforms. A well-known limitation to classical emulation of quantum circuits is scalability. Existing hardware emulators implement gate-based circuit models of quantum circuits that result in heavy resource utilization and degrade the scalability of the system. Also, current quantum emulation hardware use fixedpoint arithmetic, which has an adverse effect on accuracy when the system is scaled up. In this work, we employ a complexmultiply-and-accumulate (CMAC) and lookup-based emulation approach that greatly reduces resource utilization and improves system scalability in terms of number of emulated qubits. We demonstrate emulation of up to 16 fully-entangled qubits which is highest among existing work. We design fully-pipelined, highthroughput hardware architectures that use floating-point precision for higher accuracy. Experimental evaluation and analysis of the architectures in terms of speed and area is also provided. The emulator is prototyped on a high-performance reconfigurable computing (HPRC) system and our results demonstrate quantitative improvement over existing Field-Programmable-Gate-Array (FPGA)-based hardware emulators.
The general approach for emulating quantum algorithms on classical platforms has been through representing them as gate-based quantum circuits. However, direct implementation of quantum circuits significantly increases the hardware resource utilization and system latency of classical emulators. In this paper, we investigate multiple implementation models alternative to conventional emulation approaches, as feasible solutions to the scalability problem in classical emulation of quantum circuits. In the first model, the quantum circuit functionality is reduced to equivalent, arithmetic (multiply-and-accumulate) operations and combined with two computation methods, based on lookup and dynamic generation. In the second model, a kernel operation is extracted from the quantum circuit based on its functionality, and the kernel is iterated through all input quantum states. The proposed emulation models provide space and time optimizations, significantly reducing resource utilizations and latencies and improving scalability. We use these models to develop a highly scalable hardware emulator that is based on reconfigurable technology for efficient simulations of full quantum algorithms and circuits. Our hardware implementations support single precision floating point arithmetic for improved accuracy, and contain fully pipelined designs for high throughput. We investigate quantum algorithms such as quantum Fourier transform and quantum wavelet transform and explore different hardware architectures and optimizations. Experimental results and analysis are provided for the architectures in terms of resource consumption and emulation time. The experiments are carried out on a high-performance reconfigurable computing system and the obtained results show that the proposed emulator is feasible for running and testing a variety of quantum algorithms.
Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.
The introduction of quantum computing has led to an immense increase in performance of various search and encryption algorithms. However the practical realization of quantum computers is1a challenging task. Hence quantum algorithms are being modeled on classical platforms. Hardware emulation of quantum computers has been found to be more effective than software simulations. In this paper, Grover's search algorithm has been modeled in the classical platform using both hardware emulation and software simulation approaches. The modified architecture of the field programmable gate arrays (FPGAs) and the unique data path implemented in this paper results in considerable speed-up and lesser utilization of resources as compared to other existing works. This work includes both simulation and emulation of Grover’s search for 2,3 and 5 qubit systems. The novel emulation approach has led to a 104times reduction in time of search than the corresponding simulation.
Quantum computing (QC) leverages superposition, entanglement, and parallelism to solve complex problems that are challenging for classical computing methods. The immense potential of QC has spurred explosive interest and research in both academia and industry. However, the practicality of QC based on large-scale quantum computers remains limited by issues of scalability and error correction. To bridge this gap, QC emulators utilizing classical computing resources have emerged, with modern implementations employing FPGAs for efficiency. Nevertheless, FPGA-based QC emulators face significant limitations, particularly in standalone implementations required for low-power, low-performance devices like IoT end nodes, embedded systems, and wearable devices, due to their substantial resource demands. This paper proposes optimization techniques to reduce resource requirements and enable standalone FPGA implementations of QC emulators. We specifically focused on Grover's algorithm, known for its excellent performance in searching unstructured databases. The proposed resource-saving optimization techniques allow for the emulation of the largest possible Grover's algorithm within the constrained resources of FPGAs. Using these optimization techniques, we developed a hardware accelerator for Grover's algorithm and integrated it with a RISC-V processor architecture. We completed a standalone Grover's algorithm-specific emulator operating on FPGAs, demonstrating significant performance enhancements and resource savings afforded by the proposed techniques.