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IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)

Implementation of an Quantum Circuit Simulator using Classical Bits

Yunpyo Hong, Seokhun Jeon, Sihyeong Park, Byung-Soo Kim

Published Jun 13, 2022• 7 citations
Publisher

Abstract

The quantum computer has attracted much attention since it can reduce running time of many tasks such as factorization and search compared to classical computers. However, the actual quantum computer is difficult to get access, and the classical computer has a problem of calculation time and computation cost grows exponentially with increasing the number of qubits. In this paper, we address an efficient quantum circuit simulator including quantum circuit emulation hardware and its software framework using classical bit. Also, the proposed quantum circuit simulator operates the same as the conventional quantum software framework and shows a fast operation speed.

DOI
10.1109/aicas54282.2022.9870019

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The quantum computer has attracted much attention since it can reduce running time of many tasks such as factorization and search compared to classical computers. However, the actual quantum computer is difficult to get access, and the classical computer has a problem of calculation time and computation cost grows exponentially with increasing the number of qubits. In this paper, we address an efficient quantum circuit simulator including quantum circuit emulation hardware and its software framework using classical bit. Also, the proposed quantum circuit simulator operates the same as the conventional quantum software framework and shows a fast operation speed.
The quantum computer is emerging technology since it can resolve complex tasks such as factorization or search problem faster than classical computers. However, simulation of the quantum computer is difficult because computational load increases exponentially as the number of qubits used in the circuit is increased. This paper proposes a hardware architecture for quantum circuit simulation. To implement simulator smaller, our architecture operates based on a 1-input single gate regardless of the number of qubits used in the circuit In addition, our architecture helps to reduce simulation time by skipping calculation and data transfer. The proposed architecture is implemented on FPGA and the experimental results show that our architecture reduces 79.2% of the multiplication process when we simulate 20-qubit quantum Fourier transform with a small hardware size.
It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.
Quantum-mechanical phenomena are playing an increasing role in information processing as transistor sizes approach the nanometer level, while the securest forms of communication rely on quantum data encoding. When they involve a finite number of basis states, these phenomena can be modeled as quantum circuits, the quantum analogue of conventional or classical logic circuits. Simulation of quantum circuits can therefore be used as a tool to evaluate issues in the design of quantum information processors. Unfortunately, simulating such phenomena efficiently is exceedingly difficult. The matrices representing quantum operators (gates) and vectors modeling quantum states grow exponentially with the number of quantum bits. The information represented by quantum states and operators often exhibits structure that can be exploited when simulating certain classes of quantum circuits. We study the development of simulation methods that run on classical computers and take advantage of such repetitions and redundancies. In particular, we define a new data structure for simulating quantum circuits called the quantum information decision diagram (QuIDD). A QuIDD is a compressed graph representation of a vector or matrix and permits computations to be performed directly on the compressed data. We develop a comprehensive set of algorithms for operating on QuIDDs in both the state-vector and density-matrix formats, and evaluate their complexity. These algorithms have been implemented in a general-purpose simulator program for quantum-mechanical applications called QuIDDPro. Through extensive experiments conducted on representative quantum simulation applications, including Grover's search algorithm, error characterization, and reversible circuits, we demonstrate that QuIDDPro is faster than other existing quantum-mechanical simulators such as the National Institute of Standards and Technology's QCSim program, and is far more memory-efficient. Using QuIDDPro, we explore the advantages of quantum computation over classical computation, simulate quantum errors and error correction, and study the impact of numerical precision on the fidelity of simulations. We also develop several novel algorithms for testing quantum circuit equivalence and compare them empirically. The QuIDDPro software is equipped with a user-friendly interface and is distributed with numerous example scripts. It has been used as a laboratory supplement for quantum computing courses at several universities.
Quantum computing simulation platform can simulate the computation results of the quantum computer based on traditional computers, which is an effective way to promote the development of quantum computing software, algorithms and hardware at the current immature stage of the real quantum computer. Since quantum computers have exponential calculation acceleration compared with traditional computers, the main problems in implementing quantum computing simulation on traditional computers are low computational efficiency and long time-consuming. A quantum circuit which is a sequence of quantum gates acting on a collection of qubits is the general quantum computing model. So by the means of quantum circuit optimization, the calculation speed can be significantly increased while keeping the calculation result unchanged. The existing empirical rules of quantum circuit optimization methods have limitations and there is no common and automatic quantum circuit optimization method. In this paper, a general and automatic quantum circuit optimization method based on the genetic algorithm is proposed, by which the equivalent optimal quantum circuit is obtained through a finite number of searching in a large searching space. This method is not limited by the hardware of the quantum computing simulation and the composition of the quantum circuit. The experimental results show that for the QFT algorithm of 29 qubits, the running time can be shortened by 41.4% and for the variational circuit of 6 qubits, the running time can be shortened by 18.8% compared with the state-of-the-art quantum circuit optimization method. So this method can improve the quantum computing simulation capability and operating efficiency and provide a rapid development way for quantum algorithms and applications.
Quantum computers are regarded as the future of computing, as they are believed to be capable of solving extremely complex problems that are intractable on conventional digital computers. However, near-term quantum computers are prone to a plethora of noise sources that are difficult to mitigate, possibly limiting their scalability and precluding us from running any useful algorithms. Quantum emulation is an alternative approach that uses classical analog hardware to emulate the properties of superposition and entanglement, thereby mimicking quantum parallelism to attain similar speeds. By contrast, the use of classical digital hardware, such as field programmable gate arrays (FPGA), is less inefficient at emulating a quantum computer, as it does not take advantage of the fundamentally analog nature of quantum states. Consequently, this approach adds an inherent hardware overhead that also prevents scaling. In this work, an energy-efficient quantum emulator based on analog circuits realized in UMC 180-nm CMOS technology is proposed along with the design methodologies for a scalable computing architecture. A six-fold improvement in power consumption was observed over the FPGA-based approach for a ten-qubit emulation of Grover's search algorithm. The proposed emulator is also about 400 times faster than a Ryzen 5600x six-core processor performing a simulation of six-qubit Grover's search algorithm
While physical realization of practical large-scale quantum computers is still ongoing, theoretical research of quantum computing applications is facilitated on classical computing platforms through simulation and emulation methods. Nevertheless, the exponential increase in resource requirement with the increase in the number of qubits is an inherent issue in classical modeling of quantum systems. In the effort to alleviate the critical scalability issue in existing FPGA emulation works, a novel FPGA-based quantum circuit emulation framework based on Heisenberg representation is proposed in this paper. Unlike previous works that are restricted to the emulations of quantum circuits of small qubit sizes, the proposed FPGA emulation framework can scale-up to 120-qubit on Altera Stratix IV FPGA for the stabilizer circuit case study while providing notable speed-up over the equivalent simulation model.