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International Conference on Field-Programmable Technology (FPT)

A Table Look-Up Based Quantum Simulation Accelerator on an FPGA

Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi

Published Dec 10, 2024• 1 citation
Publisher

Abstract

In quantum computing simulation, efficient data representation is essential since a naive data representation can strain memory bandwidth and limit parallelism. This paper presents a new data representation, base-$\frac{1}{\sqrt{2}}$numeral system, to implement fast quantum computing simulation on FPGAs. The results show that our accelerator is the fastest simulator among CPU, GPU, and FPGA-based ones, providing a valuable tool for researchers developing and testing quantum algorithms.

DOI
10.1109/icfpt64416.2024.11113474

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In quantum computing simulation, efficient data representation is essential since a naive data representation can strain memory bandwidth and limit parallelism. This paper presents a new data representation, base-12\frac{1}{\sqrt{2}}2​1​numeral system, to implement fast quantum computing simulation on FPGAs. The results show that our accelerator is the fastest simulator among CPU, GPU, and FPGA-based ones, providing a valuable tool for researchers developing and testing quantum algorithms.
Practical quantum computers are still in the nascent stages of development, which makes simulation tools essential for advancing quantum algorithms. Since such a simulation involves massive parallel computations, a naive data representation can strain the memory bandwidth and limit parallelism. In this paper, we propose an FPGA-based pipelined accelerator based on the base-12\frac{1}{{\sqrt 2 }}2​1​ numeral system for quantum computer simulation. The representation of base-12\frac{1}{{\sqrt 2 }}2​1​ numbers does not require complex multipliers and adders, but only cross-bars, shifts, and customized full adders to perform the simulation, realizing higher speed. The experimental results show that our accelerator achieves 15.1-34, 009.7 × faster than CPU and GPU, and 8.4-40.7 × faster than other FPGA-based accelerators. Thus, our accelerators based on base-12\frac{1}{{\sqrt 2 }}2​1​ are the fastest simulator among CPU, GPU, and FPGA-based ones, providing a valuable tool for researchers developing and testing quantum algorithms.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.
Among the many computational models for quantum computing, the Quantum Circuit Model is the most well-known and used model for interacting with current quantum hardware. The practical implementation of quantum computers is a very active research field. Despite this progress, access to physical quantum computers remains relatively limited. Furthermore, the existing machines are susceptible to random errors due to quantum decoherence, as well as being limited in number of qubits, connectivity and built-in error correction. Simulation on classical hardware is therefore essential to allow quantum algorithm researchers to test and validate new algorithms in a simulated-error environment. Computing systems are becoming increasingly heterogeneous, using a variety of hardware accelerators to speed up computational tasks. One such type of accelerators, Field Programmable Gate Arrays (FPGAs), are reconfigurable circuits that can be programmed using standardized high-level programming models such as OpenCL and SYCL. FPGAs allow to create specialized highly-parallel circuits capable of mimicking the quantum parallelism properties of quantum gates, in particular for the class of quantum algorithms where many different computations can be performed concurrently or as part of a deep pipeline. They also benefit from very high internal memory bandwidth. This paper focuses on the analysis of quantum algorithms for applications in computational fluid dynamics. In this work we introduce novel quantum-circuit implementations of model lattice-based formulations for fluid dynamics, specifically the D1Q3 model using quantum computational basis encoding, as well as, efficient simulation of the circuits using FPGAs. This work forms a step toward quantum circuit formulation of the Lattice Boltzmann Method (LBM). For the quantum circuits implementing the nonlinear equilibrium distribution function in the D1Q3 lattice model, it is shown how circuit transformations can be introduced that facilitate the efficient simulation of the circuits on FPGAs, exploiting their fine-grained parallelism. We show that these transformations allow us to exploit more parallelism on the FPGA and improve memory locality. Preliminary results show that for this class of circuits the introduced transformations improve circuit execution time. We show that FPGA simulation of the reduced circuits results in more than 3× improvement in performance per Watt compared to the CPU simulation. We also present results from evaluating the same kernels on a GPU.
With the development of quantum algorithms and practical quantum computing devices, how to efficiently simulate emerging quantum algorithms via quantum circuit simulators on classical parallel-computing hardware platforms has raised more and more interest. The superior customized parallelism and pipeline efficiency over general-purpose processors make FPGAs ideal for large scale quantum algorithms/circuits simulation. Since the quantum Fourier transform (QFT) has been used in many quantum algorithms, such as quantum linear algebra, quantum phase estimation and quantum machine leaning, this paper presented a novel precision analysis and an efficient customized-precision QFT simulator accelerated on AMD Alveo U55C FPGAs. Customized-precision representations via high-level synthesis are employed for QFT implementation with up to 16 qubits, demonstrating up-to 8.3× speedup versus implementations in floating-point arithmetic within an error tolerance of 0.1%.
Many large-scale optimisation problems, such as those in power systems, finance and logistics can be potentially solved in the fundamentally new approach of quantum algorithms, namely Quantum Approximate Optimisation Algorithm (QAOA). In the context of fuzzy systems for instance, it is already shown that some of the intense computation associated with complex or higher-order fuzzy logic systems can be offloaded to such quantum algorithms. While the quantum computation hardware technology is still in its infancy, efficient simulations of the quantum algorithms play a crucial role in advancing quantum algorithms. The current CPU/GPU-based approaches suffer from high energy consumption and speed and scalability limitations. This paper presents the current position of our research to develop an efficient and scalable QAOA simulation based on a large network of Field-Programmable Gate Array (FPGA) modules, inspired by FPGA’s hardware-level parallelism. Although there exist a few attempts on using FPGA for general quantum circuits simulation, this project introduces a novel approach by employing a highly efficient recursive matrix decomposition algorithms specifically designed for QAOA. This work can pave the pathway a scalable and energy-efficient solution for cross-domain optimisation problems. The actual results and evaluations are to be reported in follow-up publications.
Field Programmable Gate Arrays (FPGAs) have been used in most of the physics sub-fields for various unique purposes. This includes particle physics, quantum optics, and, more recently, quantum computing. FPGAs boast many benefits over previous experimental and computational setups. They are versatile, easy to program, and cost-effective, leading to an understandable desire to incorporate them into the new field of quantum computing. While FPGAs have been used to help control the readout and control of physical qubits, they can also be a good tool for improving algorithm simulations, which is the focus of this paper. Different algorithms have different computational limits because of the varying operations and circuit depth levels. Due to the ease of incorporating parallel processes and the ability to optimize FPGAs on a deeper level, we can speed up computationally expensive operations, increasing the size of the quantum circuits we can simulate. This paper aims to provide an educational walkthrough for quantum computing physicists interested in taking advantage of FPGAs in their research. Our findings indicate that an inexpensive FPGA with a clock rate of 100MHz can perform simple, unoptimized matrix operations on the order of 107 ns faster than a CPU using optimized Python libraries. This can be further improved upon using more expensive hardware and optimized designs. This will provide many researchers and students with the tools needed to study quantum algorithms without the need for costly hardware.