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IEEE International Symposium on Multiple-Valued Logic (ISMVL)

A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation

Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi

Published Jun 5, 2025• 2 citations
Publisher

Abstract

Practical quantum computers are still in the nascent stages of development, which makes simulation tools essential for advancing quantum algorithms. Since such a simulation involves massive parallel computations, a naive data representation can strain the memory bandwidth and limit parallelism. In this paper, we propose an FPGA-based pipelined accelerator based on the base-$\frac{1}{{\sqrt 2 }}$ numeral system for quantum computer simulation. The representation of base-$\frac{1}{{\sqrt 2 }}$ numbers does not require complex multipliers and adders, but only cross-bars, shifts, and customized full adders to perform the simulation, realizing higher speed. The experimental results show that our accelerator achieves 15.1-34, 009.7 × faster than CPU and GPU, and 8.4-40.7 × faster than other FPGA-based accelerators. Thus, our accelerators based on base-$\frac{1}{{\sqrt 2 }}$ are the fastest simulator among CPU, GPU, and FPGA-based ones, providing a valuable tool for researchers developing and testing quantum algorithms.

DOI
10.1109/ismvl64713.2025.00031

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•Jul 24, 2025•0 citations
Practical quantum computers are still in the nascent stages of development, which makes simulation tools essential for advancing quantum algorithms. Since such a simulation involves massive parallel computations, a naive data representation can strain the memory bandwidth and limit parallelism. In this paper, we propose an FPGA-based pipelined accelerator based on the base-12\frac{1}{{\sqrt 2 }}2​1​ numeral system for quantum computer simulation. The representation of base-12\frac{1}{{\sqrt 2 }}2​1​ numbers does not require complex multipliers and adders, but only cross-bars, shifts, and customized full adders to perform the simulation, realizing higher speed. The experimental results show that our accelerator achieves 15.1-34, 009.7 × faster than CPU and GPU, and 8.4-40.7 × faster than other FPGA-based accelerators. Thus, our accelerators based on base-12\frac{1}{{\sqrt 2 }}2​1​ are the fastest simulator among CPU, GPU, and FPGA-based ones, providing a valuable tool for researchers developing and testing quantum algorithms.
In quantum computing simulation, efficient data representation is essential since a naive data representation can strain memory bandwidth and limit parallelism. This paper presents a new data representation, base-12\frac{1}{\sqrt{2}}2​1​numeral system, to implement fast quantum computing simulation on FPGAs. The results show that our accelerator is the fastest simulator among CPU, GPU, and FPGA-based ones, providing a valuable tool for researchers developing and testing quantum algorithms.
With the development of quantum algorithms and practical quantum computing devices, how to efficiently simulate emerging quantum algorithms via quantum circuit simulators on classical parallel-computing hardware platforms has raised more and more interest. The superior customized parallelism and pipeline efficiency over general-purpose processors make FPGAs ideal for large scale quantum algorithms/circuits simulation. Since the quantum Fourier transform (QFT) has been used in many quantum algorithms, such as quantum linear algebra, quantum phase estimation and quantum machine leaning, this paper presented a novel precision analysis and an efficient customized-precision QFT simulator accelerated on AMD Alveo U55C FPGAs. Customized-precision representations via high-level synthesis are employed for QFT implementation with up to 16 qubits, demonstrating up-to 8.3× speedup versus implementations in floating-point arithmetic within an error tolerance of 0.1%.
A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).
Since quantum computers are not readily available, much quantum computing research such as quantum algorithm verification has to be conducted on classical computer platforms. While many quantum circuit simulators have been developed on CPUs and GPUs, the potential of FPGAs as a platform with parallel computing capabilities and high energy efficiency has not been fully explored. This paper describes a novel approach with two modes of data movement optimization for an FPGA-based parallel pipelined dataflow architecture targeting a compact computation format. A data decoupling method is adapted to partition computing tasks and data into non-interacting sub- sets, significantly reducing external data interaction overhead. The proposed approach shows significant promise in improving performance and energy efficiency compared with existing state vector based CPU, GPU, and FPGA implementations.
Among the many computational models for quantum computing, the Quantum Circuit Model is the most well-known and used model for interacting with current quantum hardware. The practical implementation of quantum computers is a very active research field. Despite this progress, access to physical quantum computers remains relatively limited. Furthermore, the existing machines are susceptible to random errors due to quantum decoherence, as well as being limited in number of qubits, connectivity and built-in error correction. Simulation on classical hardware is therefore essential to allow quantum algorithm researchers to test and validate new algorithms in a simulated-error environment. Computing systems are becoming increasingly heterogeneous, using a variety of hardware accelerators to speed up computational tasks. One such type of accelerators, Field Programmable Gate Arrays (FPGAs), are reconfigurable circuits that can be programmed using standardized high-level programming models such as OpenCL and SYCL. FPGAs allow to create specialized highly-parallel circuits capable of mimicking the quantum parallelism properties of quantum gates, in particular for the class of quantum algorithms where many different computations can be performed concurrently or as part of a deep pipeline. They also benefit from very high internal memory bandwidth. This paper focuses on the analysis of quantum algorithms for applications in computational fluid dynamics. In this work we introduce novel quantum-circuit implementations of model lattice-based formulations for fluid dynamics, specifically the D1Q3 model using quantum computational basis encoding, as well as, efficient simulation of the circuits using FPGAs. This work forms a step toward quantum circuit formulation of the Lattice Boltzmann Method (LBM). For the quantum circuits implementing the nonlinear equilibrium distribution function in the D1Q3 lattice model, it is shown how circuit transformations can be introduced that facilitate the efficient simulation of the circuits on FPGAs, exploiting their fine-grained parallelism. We show that these transformations allow us to exploit more parallelism on the FPGA and improve memory locality. Preliminary results show that for this class of circuits the introduced transformations improve circuit execution time. We show that FPGA simulation of the reduced circuits results in more than 3× improvement in performance per Watt compared to the CPU simulation. We also present results from evaluating the same kernels on a GPU.
Field Programmable Gate Arrays (FPGAs) have been used in most of the physics sub-fields for various unique purposes. This includes particle physics, quantum optics, and, more recently, quantum computing. FPGAs boast many benefits over previous experimental and computational setups. They are versatile, easy to program, and cost-effective, leading to an understandable desire to incorporate them into the new field of quantum computing. While FPGAs have been used to help control the readout and control of physical qubits, they can also be a good tool for improving algorithm simulations, which is the focus of this paper. Different algorithms have different computational limits because of the varying operations and circuit depth levels. Due to the ease of incorporating parallel processes and the ability to optimize FPGAs on a deeper level, we can speed up computationally expensive operations, increasing the size of the quantum circuits we can simulate. This paper aims to provide an educational walkthrough for quantum computing physicists interested in taking advantage of FPGAs in their research. Our findings indicate that an inexpensive FPGA with a clock rate of 100MHz can perform simple, unoptimized matrix operations on the order of 107 ns faster than a CPU using optimized Python libraries. This can be further improved upon using more expensive hardware and optimized designs. This will provide many researchers and students with the tools needed to study quantum algorithms without the need for costly hardware.