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China Semiconductor Technology International Conference (CSTIC)

Precision Analysis and Hardware Acceleration for Large-Scale Quantum Fourier Transformation on Modern FPGAS

Fangtian Gu, Jiyuan Liu, He Li

Published Mar 24, 2025• 0 citations
Publisher

Abstract

With the development of quantum algorithms and practical quantum computing devices, how to efficiently simulate emerging quantum algorithms via quantum circuit simulators on classical parallel-computing hardware platforms has raised more and more interest. The superior customized parallelism and pipeline efficiency over general-purpose processors make FPGAs ideal for large scale quantum algorithms/circuits simulation. Since the quantum Fourier transform (QFT) has been used in many quantum algorithms, such as quantum linear algebra, quantum phase estimation and quantum machine leaning, this paper presented a novel precision analysis and an efficient customized-precision QFT simulator accelerated on AMD Alveo U55C FPGAs. Customized-precision representations via high-level synthesis are employed for QFT implementation with up to 16 qubits, demonstrating up-to 8.3× speedup versus implementations in floating-point arithmetic within an error tolerance of 0.1%.

DOI
10.1109/cstic64481.2025.11017853

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The Quantum Fourier Transform (QFT) has an important role in some of the most interesting and useful quantum algorithms, such as those for period finding, order finding, phase estimation and factoring. Most of the research carried out on the QFT has been developed using software simulators, however these do not emulate efficiently the quantum parallelism present in the quantum algorithms. Addressing this problem, this paper presents the hardware design of an emulator for computing the QFT using FPGAs. This emulator was designed considering a modular philosophy and it is expected to be a powerful tool to evaluate quantum algorithms that include a many-qubit QFT.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.
Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.
Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.