Reversible logic adheres to the principles of quantum computation by preventing the wasteful dissipation of energy through heat, unlike conventional calculation mired in thermodynamic inefficiency. Drawing on past frameworks, this study expands the design of reversible carry select adders to a highly scalable 256 qubit architecture. A meticulous examination of salient performance parameters such as quantum cost, spatial compactness, and energy usage is conducted for five proposed reversible CSLA designs. Advanced quantum logical techniques are employed in these architectures to maximize operational proficiency while preserving extensibility. In comparison with traditional designs, the suggested 256 qubit reversible adder achieves more refined spatial optimization and lessens quantum cost, yielding notable increases in computational prowess. It provides a pragmatic alternative for low power digital systems and high performance quantum computing by ensuring expansibility and adaptability.
Reversible logic adheres to the principles of quantum computation by preventing the wasteful dissipation of energy through heat, unlike conventional calculation mired in thermodynamic inefficiency. Drawing on past frameworks, this study expands the design of reversible carry select adders to a highly scalable 256 qubit architecture. A meticulous examination of salient performance parameters such as quantum cost, spatial compactness, and energy usage is conducted for five proposed reversible CSLA designs. Advanced quantum logical techniques are employed in these architectures to maximize operational proficiency while preserving extensibility. In comparison with traditional designs, the suggested 256 qubit reversible adder achieves more refined spatial optimization and lessens quantum cost, yielding notable increases in computational prowess. It provides a pragmatic alternative for low power digital systems and high performance quantum computing by ensuring expansibility and adaptability.
Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size. As the best outcome, this study proposes an optimized reversible adder circuit that addresses quantum propagation delay, achieving an acceptable trade-off with quantum cost compared to its counterparts. This article reduces calculation delay by 66%, 73%, 82%, and 87% for 16, 32, 64, and 128 bits, respectively, while maintaining a lower quantum cost in all cases.
Abstract: Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size.. Introduction: one of the critical factors in designing VLSI circuits and digital systems is power consumption and energy dissipation. Energy dissipation increases due to many transistors in circuits, shrinking the feature size. In the early 1960s, Landauer introduced a novel power dissipation principle in digital circuits. He issued his theory about power dissipation based on information loss during computation in digital systems. From his perspective, designing digital and logical circuits based on conventional logic, also known as irreversible logic, leads to inevitable power dissipation. The motive is that digital circuits designed based on irreversible logic contain more input lines
Reversible logic efficiently prevents energy wastage through thermal dissipation. This project presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size
Optimizing the performance metrics for the efficient circuit designs is a primary challenge for the Hardware Synthesis. Conventional logic circuits are discarded for more information loss at computation process. This introduces a new approach for the quantum reversible carry select adder(CSLA) design which includes Haghpharast-Navi gate(HNG), Feynman double gate(F2G) , and Controlled operation gate(COG). This incorporates the reverse logic principles for regaining the actual inputs from outputs. This minimizes the energy loss with refined designs for standard Boolean tasks. The operational carry select adder developed for reversible logic over the pipelined architecture for reducing the delay. To optimize the delay over non-pipelined designs, the clocked pipelining registers are introduced for intermediate processing. This allows the pre-processing by simultaneous execution in many stages. The design simulation is developed on the Xilinx Vivado tool with mixed signals like analog and digital. Performance tests demonstrate that the pipelined design remains compact, similar to standard reversible operational CSLA designs, while efficiently increasing speed which drops the delay from 7.967 ns to 4.960 ns, representing about a 63.9% improvement. These features make the proposed method ideal for high-speed quantum arithmetic applications, such as cryptographic systems and digital signal processing.
The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently perform BCD addition and implement the required correction logic while maintaining full reversibility. Evaluation results indicate that the proposed designs surpass existing reversible BCD adders, achieving best-case average improvements of 85.12% in delay and 30.75% in quantum cost. These advancements demonstrate the potential of the proposed adders for integration into future quantum-based arithmetic units and scalable reversible computing systems. Moreover, analysis of real banking transaction data underscores the practical importance of BCD addition and its widespread use in accurate and efficient monetary computations.
A reconfigurable 16-bit adder utilizing reversible logic is introduced to enhance both energy efficiency and computational performance. The design integrates Toffoli, Peres, and Haghparast–Navi Gate (HNG) to construct optimized full adder units with lower quantum cost, reduced garbage outputs, and minimal constant inputs. A reversible multiplexer is employed to enable seamless switching between Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA) configurations. While RCA mode supports power-efficient operation, CLA mode enables faster computation, allowing the circuit to adapt to different processing requirements. Performance evaluation is carried out considering propagation delay, power consumption and hardware utilization. The analysis indicates enhanced efficiency over existing reversible adder designs. Due to its adaptable structure and scalable nature, the architecture is appropriate for reversible computing, quantum systems, and low-power VLSI applications.