Reversible logic efficiently prevents energy wastage through thermal dissipation. This project presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size
Reversible logic efficiently prevents energy wastage through thermal dissipation. This project presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size
Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size. As the best outcome, this study proposes an optimized reversible adder circuit that addresses quantum propagation delay, achieving an acceptable trade-off with quantum cost compared to its counterparts. This article reduces calculation delay by 66%, 73%, 82%, and 87% for 16, 32, 64, and 128 bits, respectively, while maintaining a lower quantum cost in all cases.
Abstract: Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size.. Introduction: one of the critical factors in designing VLSI circuits and digital systems is power consumption and energy dissipation. Energy dissipation increases due to many transistors in circuits, shrinking the feature size. In the early 1960s, Landauer introduced a novel power dissipation principle in digital circuits. He issued his theory about power dissipation based on information loss during computation in digital systems. From his perspective, designing digital and logical circuits based on conventional logic, also known as irreversible logic, leads to inevitable power dissipation. The motive is that digital circuits designed based on irreversible logic contain more input lines
Reversible logic adheres to the principles of quantum computation by preventing the wasteful dissipation of energy through heat, unlike conventional calculation mired in thermodynamic inefficiency. Drawing on past frameworks, this study expands the design of reversible carry select adders to a highly scalable 256 qubit architecture. A meticulous examination of salient performance parameters such as quantum cost, spatial compactness, and energy usage is conducted for five proposed reversible CSLA designs. Advanced quantum logical techniques are employed in these architectures to maximize operational proficiency while preserving extensibility. In comparison with traditional designs, the suggested 256 qubit reversible adder achieves more refined spatial optimization and lessens quantum cost, yielding notable increases in computational prowess. It provides a pragmatic alternative for low power digital systems and high performance quantum computing by ensuring expansibility and adaptability.
Optimizing the performance metrics for the efficient circuit designs is a primary challenge for the Hardware Synthesis. Conventional logic circuits are discarded for more information loss at computation process. This introduces a new approach for the quantum reversible carry select adder(CSLA) design which includes Haghpharast-Navi gate(HNG), Feynman double gate(F2G) , and Controlled operation gate(COG). This incorporates the reverse logic principles for regaining the actual inputs from outputs. This minimizes the energy loss with refined designs for standard Boolean tasks. The operational carry select adder developed for reversible logic over the pipelined architecture for reducing the delay. To optimize the delay over non-pipelined designs, the clocked pipelining registers are introduced for intermediate processing. This allows the pre-processing by simultaneous execution in many stages. The design simulation is developed on the Xilinx Vivado tool with mixed signals like analog and digital. Performance tests demonstrate that the pipelined design remains compact, similar to standard reversible operational CSLA designs, while efficiently increasing speed which drops the delay from 7.967 ns to 4.960 ns, representing about a 63.9% improvement. These features make the proposed method ideal for high-speed quantum arithmetic applications, such as cryptographic systems and digital signal processing.
Reversible logic is one of the emerging technologies having promising applications in quantum computing. In this work, we present new design of the reversible BCD adder that has been primarily optimized for the number of ancilla input bits and the number of garbage outputs. The number of ancilla input bits and the garbage outputs is primarily considered as an optimization criteria as it is extremely difficult to realize a quantum computer with many qubits. As the optimization of ancilla input bits and the garbage outputs may degrade the design in terms of the quantum cost and the delay, thus the quantum cost and the delay parameters are also considered for optimization with primary focus towards the optimization of the number of ancilla input bits and the garbage outputs. Firstly, we propose a new design of the reversible ripple carry adder having the input carry Co and is designed with no ancilla input bits. The proposed reversible ripple carry adder design with no ancilla input bits has less quantum cost and the logic depth (delay) compared to its existing counterparts. The existing reversible Peres gate and a new reversible gate called the TR gate is efficiently utilized to improve the quantum cost and the delay of the reversible ripple carry adder. The improved quantum design of the TR gate is also illustrated. Finally, the reversible design of the BCD adder is presented which is based on a 4 bit reversible binary adder to add the BCD number, and finally the conversion of the binary result to the BCD format using a reversible binary to BCD converter.
With the advent of nanotechnology, transistors are getting smaller and growing in number according to Moore's Law. With this, the issue of heat dissipation is becoming of greater concern to researchers as the transistor heat dissipation reaches the Land Auer limit. Reversible logic is predicted to be an alternative to conventional computing due to lesser energy dissipation and exponentially faster problem-solving capacity. This paper introduces the design of a reversible ripple-carry adder using a mix of the well-known NCV library and the recently introduced NCV-|v1> library, with the assumption of a four-level quantum system. The results for the proposed adder are compared with previous ripple-carry adder designs. It then explores the design of a cost-optimized reversible ALU by modifying the above adder. Finally, a comparison of the proposed ALU is made with one of the latest reversible ALU designs.