Abstract: Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size.. Introduction: one of the critical factors in designing VLSI circuits and digital systems is power consumption and energy dissipation. Energy dissipation increases due to many transistors in circuits, shrinking the feature size. In the early 1960s, Landauer introduced a novel power dissipation principle in digital circuits. He issued his theory about power dissipation based on information loss during computation in digital systems. From his perspective, designing digital and logical circuits based on conventional logic, also known as irreversible logic, leads to inevitable power dissipation. The motive is that digital circuits designed based on irreversible logic contain more input lines
Abstract: Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size.. Introduction: one of the critical factors in designing VLSI circuits and digital systems is power consumption and energy dissipation. Energy dissipation increases due to many transistors in circuits, shrinking the feature size. In the early 1960s, Landauer introduced a novel power dissipation principle in digital circuits. He issued his theory about power dissipation based on information loss during computation in digital systems. From his perspective, designing digital and logical circuits based on conventional logic, also known as irreversible logic, leads to inevitable power dissipation. The motive is that digital circuits designed based on irreversible logic contain more input lines
Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size. As the best outcome, this study proposes an optimized reversible adder circuit that addresses quantum propagation delay, achieving an acceptable trade-off with quantum cost compared to its counterparts. This article reduces calculation delay by 66%, 73%, 82%, and 87% for 16, 32, 64, and 128 bits, respectively, while maintaining a lower quantum cost in all cases.
Reversible logic efficiently prevents energy wastage through thermal dissipation. This project presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size
Optimizing the performance metrics for the efficient circuit designs is a primary challenge for the Hardware Synthesis. Conventional logic circuits are discarded for more information loss at computation process. This introduces a new approach for the quantum reversible carry select adder(CSLA) design which includes Haghpharast-Navi gate(HNG), Feynman double gate(F2G) , and Controlled operation gate(COG). This incorporates the reverse logic principles for regaining the actual inputs from outputs. This minimizes the energy loss with refined designs for standard Boolean tasks. The operational carry select adder developed for reversible logic over the pipelined architecture for reducing the delay. To optimize the delay over non-pipelined designs, the clocked pipelining registers are introduced for intermediate processing. This allows the pre-processing by simultaneous execution in many stages. The design simulation is developed on the Xilinx Vivado tool with mixed signals like analog and digital. Performance tests demonstrate that the pipelined design remains compact, similar to standard reversible operational CSLA designs, while efficiently increasing speed which drops the delay from 7.967 ns to 4.960 ns, representing about a 63.9% improvement. These features make the proposed method ideal for high-speed quantum arithmetic applications, such as cryptographic systems and digital signal processing.
Reversible logic adheres to the principles of quantum computation by preventing the wasteful dissipation of energy through heat, unlike conventional calculation mired in thermodynamic inefficiency. Drawing on past frameworks, this study expands the design of reversible carry select adders to a highly scalable 256 qubit architecture. A meticulous examination of salient performance parameters such as quantum cost, spatial compactness, and energy usage is conducted for five proposed reversible CSLA designs. Advanced quantum logical techniques are employed in these architectures to maximize operational proficiency while preserving extensibility. In comparison with traditional designs, the suggested 256 qubit reversible adder achieves more refined spatial optimization and lessens quantum cost, yielding notable increases in computational prowess. It provides a pragmatic alternative for low power digital systems and high performance quantum computing by ensuring expansibility and adaptability.
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Next, a novel 3*3 programmable UPG gate capable of calculating the fundamental logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, nbit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, 4*4 reversible gate is presented and verified which is capable of producing the calculations necessary for two-bit comparisons. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. Then, two novel 4*4 reversible logic gates (MRG and PAOG) are proposed with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. A 5*5 structure (MG) is proposed that extends the capabilities of both the MRG and PAOG. The comparator designs are verified and its advantages to previous designs are discussed. Then, reversible implementations of ripple-carry, carry-select and Kogge-Stone carry look-ahead adders are analyzed and compared. Next, implementations of the Kogge-Stone adder with sparsity-4, 8 and 16 were designed, verified and compared. The enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders was selected as the best design, and its implemented in the design of a 32-bit arithmetic logic unit is demonstrated. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed.
In recent years, reversible logic has emerged as a promising technology withapplications spanning low-power CMOS, quantum computing, nanotechnology, andoptical computing. Quantum computing, in particular, relies on reversible logic for itsrealization. The construction of low-power and low-loss computational structures iscrucial for developing arithmetic circuits used in quantum computation, nanotechnology,and other low-power digital circuits. This work presents optimized one-digit BCD addersand carries skip BCD adders using new reversible logic gates. The proposed approachaims to minimize quantum cost and optimize performance compared to existing circuits,focusing on reducing the number of reversible gates used and minimizing garbage outputsproduced. The objective is to design faster BCD adders and provide a foundation forbuilding the decimal Arithmetic Logic Unit (ALU) of a Quantum CPU. The work isimplemented using Hardware Description Language (HDL), with Simulation & Synthesisconducted on Xilinx ISE. The design targets the Xilinx Spartan 3E FPGA device. Thisresearch contributes to the advancement of efficient and high-performance arithmeticcircuits suitable for emerging technologies such as quantum computing andnanotechnology.