Optimizing the performance metrics for the efficient circuit designs is a primary challenge for the Hardware Synthesis. Conventional logic circuits are discarded for more information loss at computation process. This introduces a new approach for the quantum reversible carry select adder(CSLA) design which includes Haghpharast-Navi gate(HNG), Feynman double gate(F2G) , and Controlled operation gate(COG). This incorporates the reverse logic principles for regaining the actual inputs from outputs. This minimizes the energy loss with refined designs for standard Boolean tasks. The operational carry select adder developed for reversible logic over the pipelined architecture for reducing the delay. To optimize the delay over non-pipelined designs, the clocked pipelining registers are introduced for intermediate processing. This allows the pre-processing by simultaneous execution in many stages. The design simulation is developed on the Xilinx Vivado tool with mixed signals like analog and digital. Performance tests demonstrate that the pipelined design remains compact, similar to standard reversible operational CSLA designs, while efficiently increasing speed which drops the delay from 7.967 ns to 4.960 ns, representing about a 63.9% improvement. These features make the proposed method ideal for high-speed quantum arithmetic applications, such as cryptographic systems and digital signal processing.
Optimizing the performance metrics for the efficient circuit designs is a primary challenge for the Hardware Synthesis. Conventional logic circuits are discarded for more information loss at computation process. This introduces a new approach for the quantum reversible carry select adder(CSLA) design which includes Haghpharast-Navi gate(HNG), Feynman double gate(F2G) , and Controlled operation gate(COG). This incorporates the reverse logic principles for regaining the actual inputs from outputs. This minimizes the energy loss with refined designs for standard Boolean tasks. The operational carry select adder developed for reversible logic over the pipelined architecture for reducing the delay. To optimize the delay over non-pipelined designs, the clocked pipelining registers are introduced for intermediate processing. This allows the pre-processing by simultaneous execution in many stages. The design simulation is developed on the Xilinx Vivado tool with mixed signals like analog and digital. Performance tests demonstrate that the pipelined design remains compact, similar to standard reversible operational CSLA designs, while efficiently increasing speed which drops the delay from 7.967 ns to 4.960 ns, representing about a 63.9% improvement. These features make the proposed method ideal for high-speed quantum arithmetic applications, such as cryptographic systems and digital signal processing.
Abstract: Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size.. Introduction: one of the critical factors in designing VLSI circuits and digital systems is power consumption and energy dissipation. Energy dissipation increases due to many transistors in circuits, shrinking the feature size. In the early 1960s, Landauer introduced a novel power dissipation principle in digital circuits. He issued his theory about power dissipation based on information loss during computation in digital systems. From his perspective, designing digital and logical circuits based on conventional logic, also known as irreversible logic, leads to inevitable power dissipation. The motive is that digital circuits designed based on irreversible logic contain more input lines
Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size. As the best outcome, this study proposes an optimized reversible adder circuit that addresses quantum propagation delay, achieving an acceptable trade-off with quantum cost compared to its counterparts. This article reduces calculation delay by 66%, 73%, 82%, and 87% for 16, 32, 64, and 128 bits, respectively, while maintaining a lower quantum cost in all cases.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
Reversible logic gates are essential for quantum computing and low-power digital circuits as they enable the recovery of input signals from output signals, thereby minimizing energy dissipation. This field of study has become a leading-edge research domain, driving innovative advancements focused on optimizing resource efficiency. This study introduces an efficient 8-bit adder/subtractor circuit designed using Feynman and HNG reversible logic gates. The circuit incorporates a control bit (M) that dictates its operational mode: M=0 signifies addition functionality, while M=1 indicates subtraction functionality. This dual functionality is achieved with substantial efficiency enhancements, as evidenced by a 22% decrease in quantum cost compared to traditional methods. The design also boasts a reduced total reversible logic implementation cost, underscoring its efficiency. Validation and simulation of the reversible 8-bit adder/subtractor circuit are conducted using Xilinx Vivado 2022.2 software
Reversible logic adheres to the principles of quantum computation by preventing the wasteful dissipation of energy through heat, unlike conventional calculation mired in thermodynamic inefficiency. Drawing on past frameworks, this study expands the design of reversible carry select adders to a highly scalable 256 qubit architecture. A meticulous examination of salient performance parameters such as quantum cost, spatial compactness, and energy usage is conducted for five proposed reversible CSLA designs. Advanced quantum logical techniques are employed in these architectures to maximize operational proficiency while preserving extensibility. In comparison with traditional designs, the suggested 256 qubit reversible adder achieves more refined spatial optimization and lessens quantum cost, yielding notable increases in computational prowess. It provides a pragmatic alternative for low power digital systems and high performance quantum computing by ensuring expansibility and adaptability.