Reversible logic gates are essential for quantum computing and low-power digital circuits as they enable the recovery of input signals from output signals, thereby minimizing energy dissipation. This field of study has become a leading-edge research domain, driving innovative advancements focused on optimizing resource efficiency. This study introduces an efficient 8-bit adder/subtractor circuit designed using Feynman and HNG reversible logic gates. The circuit incorporates a control bit (M) that dictates its operational mode: M=0 signifies addition functionality, while M=1 indicates subtraction functionality. This dual functionality is achieved with substantial efficiency enhancements, as evidenced by a 22% decrease in quantum cost compared to traditional methods. The design also boasts a reduced total reversible logic implementation cost, underscoring its efficiency. Validation and simulation of the reversible 8-bit adder/subtractor circuit are conducted using Xilinx Vivado 2022.2 software
Reversible logic gates are essential for quantum computing and low-power digital circuits as they enable the recovery of input signals from output signals, thereby minimizing energy dissipation. This field of study has become a leading-edge research domain, driving innovative advancements focused on optimizing resource efficiency. This study introduces an efficient 8-bit adder/subtractor circuit designed using Feynman and HNG reversible logic gates. The circuit incorporates a control bit (M) that dictates its operational mode: M=0 signifies addition functionality, while M=1 indicates subtraction functionality. This dual functionality is achieved with substantial efficiency enhancements, as evidenced by a 22% decrease in quantum cost compared to traditional methods. The design also boasts a reduced total reversible logic implementation cost, underscoring its efficiency. Validation and simulation of the reversible 8-bit adder/subtractor circuit are conducted using Xilinx Vivado 2022.2 software
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
Reversible logic is gaining increasing significance in diverse research areas, including quantum computing, nanotechnology, and optical computing. The exploration of reversible gates has emerged as a cutting-edge research area, driving a wave of innovative developments aimed at maximizing resource efficiency. This work focused on creating highly efficient 2-bit, 8-bit, and 64-bit comparators, leveraging the advantages of reversible logic gates. The results obtained from the comparative analysis demonstrate substantial improvements in energy efficiency and computational speed compared to other architectures. The proposed design demonstrated superior performance with reduced quantum cost and delay while minimizing garbage outputs. Specifically, the quantum costs of the 2-bit, 8-bit, and 64-bit comparators were measured to be 20, 128, and 1136, respectively. These outcomes suggest substantial enhancements in a variety of parameters, which ultimately will result in a more efficient and effective design. The functionality of the designed comparator tree was validated using Xilinx Vivado 2022.2 and implemented in Verilog HDL.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.