© 2026 Aqora Quantum S.A.S.

Terms Privacy Legal Notice

Superconductor Science and Technology

A high voltage and high speed superconductive voltage driver using a damped asymmetric DC SQUID array

Mengfei Zhao, Yongliang Wang, Xiaoping Gao, Pusheng Yuan, Shuna Wang, Minghui Niu, Lixing You, Jie Ren, Lingyun Li

Published Mar 11, 2025• 2 citations

Abstract

Abstract We present a non-return-to-zero (NRZ) superconductive voltage driver (SVD) for interfacing single flux quantum (SFQ) circuits with semiconductor circuits. The NRZ SVD design consists an encoding module, splitter networks, sixteen RS flip-flops (RSFFs), and a sixteen-stage DC SQUID array (DSA). By employing an asymmetric SQUID structure, the SVD achieved a simulated output swing of 4.3 mV. The impedance and quality factor formulas of the DSA were provided. We solved the issue of slower fall time caused by the asymmetric SQUID by inserting a termination resistor into the DSA to reduce its quality factor. By using this damped asymmetric DSA, the NRZ SVD can reach up to 30 Gbps in simulation. The test chip of the NRZ SVD was fabricated using the SIMIT’s Nb03P process (JC = 6 kA cm−2) and measured in a liquid helium dewar. The SVD achieved a measured output swing of up to 6.8 mV, which is relatively high compared to the published reports. Eye diagrams at 5 Gbps and 10 Gbps were clearly opened, demonstrating a very low bit error rate. The test circuit for the NRZ SVD can support up to 15 Gbps with a 2 9 − 1 pseudo-random bit sequence (PRBS-9) input and 20 Gbps with a sinusoidal input.

DOI: 10.1088/1361-6668/adbf54

Related papers

Measurement of Superconductive Voltage Drivers up to 25 Gb/s/ch

Y. Hashimoto, Hideo Suzuki, Shuichi Nagasawa +3 more

We report on demonstrations of a superconductive voltage driver (SVD), which generates non-return-to-zero (NRZ) output with an SFQ pulse input, up to 25 Gb/s/ch. The NRZ SVD consists of a coding logic, splitters, buffers, sixteen RS flip-flops (RSFFs), and DC-biased serially connected sixteen 2-junction SQUIDs. Each SQUID is magnetically coupled to the storage loop of each RSFF. The coding logic generates the true and complement signals of the SVD's input data, and the true and complement signals are split into sixteen with the splitters, amplified with the buffers, and applied to the RSFFs as the set and reset signals, respectively. With this configuration, the SQUIDs generate about 2-mV-high NRZ output voltage. The NRZ SVD was fabricated with our 10-kA/cm2Nb process and measured with our cryocooled system. Eye diagram of the NRZ SVD measured at 25 Gb/s/ch clearly opened, indicating low-bit-error-rate (BER) operation. Measured BER was less than 1times10-13at 20 Gb/s/ch for 27-1 pseudo-random bit sequence input.

IEEE Transactions on Applied Superconductivity•May 27, 2009•10 citations

High Voltage Driver for RSFQ Digital Signal Processor

Igor I. Soloviev, M R Rafique, Henrik Engseth +1 more

We present an Rapid Single Flux Quantum (RSFQ) based high voltage driver (HVD) developed for the first amplification stage of a hybrid semiconductor-superconductor memory interface for the RSFQ digital signal processor. Implementation of the driver allows to eliminate the impedance mismatch between RSFQ and standard 50 Omega input of semiconductor electronics and increases the signal-to-noise ratio to reach reliable signal transmission with sufficiently low bit error rate. The driver design is based on the serial stack of 8 SQUIDs with specially configured ground-cuts that form a quasi-coplanar line with 50 Omega impedance. The impedance of the driver has been extracted using 3D EM simulators that accurately take into account multilayer structure and capacitance to the ground. The circuit has been designed for the Hypres 4.5 kA/cm2process. The driver was simulated numerically in PSCAN. The driver can produce output signal at 1 Gbit/s speed and 2.4 mV signal level that is enough to be sensed by low-noise amplifier on the further amplification stage.

IEEE Transactions on Applied Superconductivity•Jun 1, 2007•12 citations

Enhanced voltage swing of rapid-single-flux-quantum distributed output amplifier equipped with double-stack superconducting quantum interference devices

Yoshinao Mizugaki, Komei Higuchi, Hiroshi Shimada

We report the enhanced voltage swing of a rapid-single-flux-quantum (RSFQ) distributed amplifier by replacing a single superconducting quantum interference device (SQUID) with a double-stack-SQUID (DSS). A DSS is composed of two stacked 2-junction SQUIDs sharing one sensing inductor. Thanks to its stack structure, a DSS is expected to generate twofold output voltage. We have designed a 12-stage RSFQ distributed amplifier equipped with DSSs. The maximum output voltage swing reached 10.2 mV in simulation. Test chips were fabricated using a 25-µA/µm2 Nb integration process. In measurements, a test chip was cooled in a liquid helium bath. The experimental output voltage swing was up to 8.34 mV.

IEICE Electronics Express•Jan 1, 2019•1 citation

Design and operation of distributed double-SQUID amplifier for RSFQ circuits

Komei Higuchi, Hiroshi Shimada, Yoshinao Mizugaki

Recently, many groups have been developing on-chip Rapid Single-Flux-Quantum (RSFQ) output amplifiers which are designed to connect RSFQ circuitry to room temperature electronics. One of such amplifiers is a distributed SQUID amplifier comprising SQUIDs embedded in cascaded RSFQ RS flip-flops. In this paper, we propose a distributed double-SQUID amplifier, where a SQUID is replaced with a double-SQUID. Test circuit was fabricated using a niobium integration technology. Measurements were performed in a liquid helium bath. We confirmed that the maximum output voltage swing of a 4-stage distributed double- SQUID amplifier was 2.93 mV, which was comparable with the corresponding numerical value of 3.54 mV.

Journal of Physics Conference Series•Sep 1, 2019•3 citations

Superconductor-to-Semiconductor Interface Circuit for High Data Rates

Thomas Ortlepp, S. Wünsch, M. Schubert +7 more

We present a new kind of rapid-single-flux-quantum (RSFQ) output driver together with a pseudomorphic high electron mobility transistor (p-HEMT) amplifier both operating at liquid helium temperature. The passive interconnect including the interchip connection between the RSFQ output driver and the first transistor stage of the semiconductor amplifier is the key element for signal matching and was optimized for minimizing the reflections to the RSFQ circuit. The RSFQ output driver is based on a single-flux-quantum to dc converter and a voltage doubler. The circuit is realized in the Niobium based 1 kA/cm2process of FLUXONICS Foundry and provides up to 438-muV output voltage. We demonstrate high-speed experiments of the output driver in combination with two different semiconductor amplifier circuits at liquid helium temperature. The output voltage of a 2-Gb/s data stream was measured to be about 3.5 mV.

IEEE Transactions on Applied Superconductivity•Jan 20, 2009•33 citations

Josephson output interfaces for RSFQ circuits

Oleg A. Mukhanov, Sergey V. Rylov, Dmitri V. Gaidarenko +2 more

We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RSFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gb/s for a (2/sup 31/-1) bit long pseudo-random bit sequence (PRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•85 citations

Abstract We present a non-return-to-zero (NRZ) superconductive voltage driver (SVD) for interfacing single flux quantum (SFQ) circuits with semiconductor circuits. The NRZ SVD design consists an encoding module, splitter networks, sixteen RS flip-flops (RSFFs), and a sixteen-stage DC SQUID array (DSA). By employing an asymmetric SQUID structure, the SVD achieved a simulated output swing of 4.3 mV. The impedance and quality factor formulas of the DSA were provided. We solved the issue of slower fall time caused by the asymmetric SQUID by inserting a termination resistor into the DSA to reduce its quality factor. By using this damped asymmetric DSA, the NRZ SVD can reach up to 30 Gbps in simulation. The test chip of the NRZ SVD was fabricated using the SIMIT’s Nb03P process (JC = 6 kA cm−2) and measured in a liquid helium dewar. The SVD achieved a measured output swing of up to 6.8 mV, which is relatively high compared to the published reports. Eye diagrams at 5 Gbps and 10 Gbps were clearly opened, demonstrating a very low bit error rate. The test circuit for the NRZ SVD can support up to 15 Gbps with a 2 9 − 1 pseudo-random bit sequence (PRBS-9) input and 20 Gbps with a sinusoidal input.

We report on demonstrations of a superconductive voltage driver (SVD), which generates non-return-to-zero (NRZ) output with an SFQ pulse input, up to 25 Gb/s/ch. The NRZ SVD consists of a coding logic, splitters, buffers, sixteen RS flip-flops (RSFFs), and DC-biased serially connected sixteen 2-junction SQUIDs. Each SQUID is magnetically coupled to the storage loop of each RSFF. The coding logic generates the true and complement signals of the SVD's input data, and the true and complement signals are split into sixteen with the splitters, amplified with the buffers, and applied to the RSFFs as the set and reset signals, respectively. With this configuration, the SQUIDs generate about 2-mV-high NRZ output voltage. The NRZ SVD was fabricated with our 10-kA/cm2Nb process and measured with our cryocooled system. Eye diagram of the NRZ SVD measured at 25 Gb/s/ch clearly opened, indicating low-bit-error-rate (BER) operation. Measured BER was less than 1times10-13at 20 Gb/s/ch for 27-1 pseudo-random bit sequence input.

We present an Rapid Single Flux Quantum (RSFQ) based high voltage driver (HVD) developed for the first amplification stage of a hybrid semiconductor-superconductor memory interface for the RSFQ digital signal processor. Implementation of the driver allows to eliminate the impedance mismatch between RSFQ and standard 50 Omega input of semiconductor electronics and increases the signal-to-noise ratio to reach reliable signal transmission with sufficiently low bit error rate. The driver design is based on the serial stack of 8 SQUIDs with specially configured ground-cuts that form a quasi-coplanar line with 50 Omega impedance. The impedance of the driver has been extracted using 3D EM simulators that accurately take into account multilayer structure and capacitance to the ground. The circuit has been designed for the Hypres 4.5 kA/cm2process. The driver was simulated numerically in PSCAN. The driver can produce output signal at 1 Gbit/s speed and 2.4 mV signal level that is enough to be sensed by low-noise amplifier on the further amplification stage.

We report the enhanced voltage swing of a rapid-single-flux-quantum (RSFQ) distributed amplifier by replacing a single superconducting quantum interference device (SQUID) with a double-stack-SQUID (DSS). A DSS is composed of two stacked 2-junction SQUIDs sharing one sensing inductor. Thanks to its stack structure, a DSS is expected to generate twofold output voltage. We have designed a 12-stage RSFQ distributed amplifier equipped with DSSs. The maximum output voltage swing reached 10.2 mV in simulation. Test chips were fabricated using a 25-µA/µm2 Nb integration process. In measurements, a test chip was cooled in a liquid helium bath. The experimental output voltage swing was up to 8.34 mV.

Recently, many groups have been developing on-chip Rapid Single-Flux-Quantum (RSFQ) output amplifiers which are designed to connect RSFQ circuitry to room temperature electronics. One of such amplifiers is a distributed SQUID amplifier comprising SQUIDs embedded in cascaded RSFQ RS flip-flops. In this paper, we propose a distributed double-SQUID amplifier, where a SQUID is replaced with a double-SQUID. Test circuit was fabricated using a niobium integration technology. Measurements were performed in a liquid helium bath. We confirmed that the maximum output voltage swing of a 4-stage distributed double- SQUID amplifier was 2.93 mV, which was comparable with the corresponding numerical value of 3.54 mV.

We present a new kind of rapid-single-flux-quantum (RSFQ) output driver together with a pseudomorphic high electron mobility transistor (p-HEMT) amplifier both operating at liquid helium temperature. The passive interconnect including the interchip connection between the RSFQ output driver and the first transistor stage of the semiconductor amplifier is the key element for signal matching and was optimized for minimizing the reflections to the RSFQ circuit. The RSFQ output driver is based on a single-flux-quantum to dc converter and a voltage doubler. The circuit is realized in the Niobium based 1 kA/cm2process of FLUXONICS Foundry and provides up to 438-muV output voltage. We demonstrate high-speed experiments of the output driver in combination with two different semiconductor amplifier circuits at liquid helium temperature. The output voltage of a 2-Gb/s data stream was measured to be about 3.5 mV.

We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RSFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gb/s for a (2/sup 31/-1) bit long pseudo-random bit sequence (PRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.