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IEEE Transactions on Applied Superconductivity

Josephson output interfaces for RSFQ circuits

Oleg A. Mukhanov, Sergey V. Rylov, Dmitri V. Gaidarenko, Noshir Dubash, V. Borzenets

Published Jun 1, 1997• 85 citations
Publisher

Abstract

We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RSFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gb/s for a (2/sup 31/-1) bit long pseudo-random bit sequence (PRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.

DOI
10.1109/77.621825

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We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RSFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gb/s for a (2/sup 31/-1) bit long pseudo-random bit sequence (PRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.
We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RsFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gbls for a (Z3l -1) bit long pseudo-random bit sequence (PPRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.
We have developed and tested simple and inexpensive electronics for interfacing Rapid Single-Flux-Quantum (RSFQ) Josephson-junction circuits to room temperature digital systems. Voltage-level (Non-Return-to-Zero) bit signals with a swing of /spl sim/150 uV, developed on-chip by standard SFQ/DC converters, and in some cases amplified to 1.5 mV swing by HUFFLE-type circuits, are passed to the 300 K environment using a high density (40 channel) flexible coplanar waveguide assembly. AC-coupled, 2-3 stage microwave Si-bipolar amps, and Emitter-Coupled-Logic (ECL) buffers accomplish voltage level translation to the standard ECL levels, Using this technique, data rates in excess of 1 Gb/s per channel can be achieved at low cost per channel,.>
The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.
The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
We have been developing an RSFQ-CMOS interface system. The system consists of three modules: a 1 to 32 bit DDST demultiplexer which converts a 16 Gb/s SFQ data input into a 32-channel 500 Mb/s output, asynchronous stacked-SQUID amplifiers which amplify an SFQ data input into a 5 mV voltage level output, and 77 K CMOS amplifiers which amplify a 5 mV voltage level input into a 5 V output at 500 MHz. We have implemented the asynchronous stacked-SQUID amplifier and the 77 K CMOS amplifier using the HYPRES 1 kA/cm/sup 2/ Nb process and the ROHM 0.6 /spl mu/m CMOS process, respectively. It was demonstrated that the 24-stage asynchronous stacked-SQUID amplifier amplifies an SFQ data input into a 2.0 mV voltage level at 600 MHz. The 77 K CMOS amplifier was shown to amplify a 5 mV voltage level input into 5 V at 500 MHz from the simulation, and a 175 mV voltage input into 3.5 V at 90 MHz from the experiment.