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IEEE Transactions on Applied Superconductivity

Superconducting Switching Amplifiers for High Speed Digital Data Links

Amol Inamdar, Sergey V. Rylov, Saad M. Sarwana, Deepnarayan Gupta

Published Jun 1, 2009• 36 citations
Publisher

Abstract

In a superconductor digital-RF transmitter, the power amplifier chain can be implemented in hybrid temperature, hybrid technology environment, where the superconductor switching amplifier forms the first stage of the amplification chain. We have designed several flavors of SQUID based switching amplifiers, each targeted for different power output and speed. One of the amplifiers is a differential amplifier featuring dynamic equalization. To minimize the intersymbol interference, the amplifier employs a pre-emphasis technique, thereby compensating for the bandwidth limitations of the channel. The differential output voltage of this amplifier is 16 mV at low speed (200 Mbps), which rolls off to 2 mV at 16 Gbps data rate, for an “1100” pattern (no consecutive transitions on the input data sequence). For high speed operation of the SQUID amplifiers, simultaneous switching of SQUIDs is desired to reduce the output rise and fall times. Hence, in another amplifier design, called the Differential H-Tree Amplifier, the SQUIDs are arranged in an “H-tree” structure, to equalize the propagation delay of the control signal to each SQUID. The amplifier's differential output voltage is 8 mV at low speed (200 Mbps), and rolls off to 2 mV at 10 Gbps data rate. A third type of amplifier is a differential SFQ-to-DC amplifier; it consists of a pair of synchronously driven SFQ-to-DC converters that produce complementary positive and negative voltage waveforms respectively. The differential output voltage of this amplifier is 0.8 mV, and it can be operated at very high speeds. Moreover, the complexity of this amplifier enables it to be yielded in higher critical current density process. Both, the speed and the output voltage scale as the square root of the process critical current density.

DOI
10.1109/tasc.2009.2018413

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In a superconductor digital-RF transmitter, the power amplifier chain can be implemented in hybrid temperature, hybrid technology environment, where the superconductor switching amplifier forms the first stage of the amplification chain. We have designed several flavors of SQUID based switching amplifiers, each targeted for different power output and speed. One of the amplifiers is a differential amplifier featuring dynamic equalization. To minimize the intersymbol interference, the amplifier employs a pre-emphasis technique, thereby compensating for the bandwidth limitations of the channel. The differential output voltage of this amplifier is 16 mV at low speed (200 Mbps), which rolls off to 2 mV at 16 Gbps data rate, for an “1100” pattern (no consecutive transitions on the input data sequence). For high speed operation of the SQUID amplifiers, simultaneous switching of SQUIDs is desired to reduce the output rise and fall times. Hence, in another amplifier design, called the Differential H-Tree Amplifier, the SQUIDs are arranged in an “H-tree” structure, to equalize the propagation delay of the control signal to each SQUID. The amplifier's differential output voltage is 8 mV at low speed (200 Mbps), and rolls off to 2 mV at 10 Gbps data rate. A third type of amplifier is a differential SFQ-to-DC amplifier; it consists of a pair of synchronously driven SFQ-to-DC converters that produce complementary positive and negative voltage waveforms respectively. The differential output voltage of this amplifier is 0.8 mV, and it can be operated at very high speeds. Moreover, the complexity of this amplifier enables it to be yielded in higher critical current density process. Both, the speed and the output voltage scale as the square root of the process critical current density.
A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.
User-friendly ultra-high-speed readout electronics for dc superconducting quantum interference devices (SQUIDs) are presented. To maximize the system bandwidth, the SQUID is directly read out without flux modulation. A composite preamplifier is used consisting of a slow dc amplifier in parallel with a fast ac amplifier. In this way, excellent dc precision and a high amplifier bandwidth of 50 MHz are achieved, simultaneously. A virtual 50 Ω amplifier input resistance with negligible excess noise is realized by active shunting, i.e., by applying feedback from preamplifier output to input via a high resistance. The white voltage and current noise levels are 0.33 nV Hz −1 and 2.6 pA Hz −1/2 , respectively. The electronics is fully computer controlled via a microcontroller integrated into the flux-locked loop (FLL) board. Easy-to-use software makes the various electronic settings accessible. A wide bias voltage range of 1.3 mV enables the readout of series SQUID arrays. Furthermore, additional current sources allow the operation of two-stage SQUIDs or transition edge sensors. The electronics was tested using various SQUIDs with input inductances between 30 nH and 1.5 µH. Typically, the maximum FLL bandwidth was 20 MHz, which is close to the theoretical limit given by transmission line delay within the FLL. Slew rates of up to 4.6 Φ 0 µs −1 were achieved with series SQUID arrays. Current noise levels as low as 0.47 pA Hz −1/2 and coupled energy sensitivities between 90 h and 500 h were measured at 4.2 K, where h is the Planck constant. The noise did not degrade when the system bandwidth was increased to the maximum value of about 20 MHz. With a two-stage set-up, intrinsic white energy sensitivities of 30 h and 2.3 h were measured at 4.2 and 0.3 K, respectively.
Efficiently amplifying the high-speed and low-voltage swing outputs of single flux quantum (SFQ) logic to levels that are suitable for interfacing with room temperature electronics has been a long-standing challenge in the field of superconducting electronics. In this work, we investigate the feasibility of using a lossy passive matching network at 4 K, with a pair of differential 100 low-noise amplifiers heatsunk to 18 K and 50 K stages, respectively. The amplifiers were implemented in a 120 nm SiGe BiCMOS technology. The amplification chain is dc coupled and the small-signal link gain was measured to be approximately 48 dB. The power consumption of each of the two amplification stages was 6.3 mW. The chain was measured at 21 K using a high-speed differential nonreturn-to-zero signal having amplitude commensurate with what one would expect from a superconducting circuit, and clean eye diagrams were observed for data rates as high as 30 Gb/s. The chain was also measured when driven from an SFQ/dc interface, with the first gain stage heatsunk to 9 K. In this configuration, clean eye diagrams were observed to 5 Gb/s, with the speed limitation being related to packaging parasitics.
We describe a low-noise, two-stage dc Superconducting QUantum Interference Device (SQUID) amplifier that is designed for applications requiring high bandwidth and dynamic range. The output signal of a low-noise SQUID in the input stage coherently modulates a series array of identical SQUIDs in the output stage via a common modulation line. The input stage is designed so its output signal does not produce multiple modulation periods in the output stage. The output stage is designed to have sufficient gain so the output noise is dominated by the amplified noise of the input SQUID and exceeds the noise of a preamplifier in the room temperature readout electronics. The SQUID amplifier may therefore be operated without flux modulation or any impedance matching network, resulting in a large dynamic range and high bandwidth.
Data transmission from single flux quantum (SFQ) circuits to room temperature electronics requires the use of superconductor output drivers and semiconductor amplifiers. The state-of-the-art superconductor output drivers such as SFQ-to-DC converter, superconducting quantum interference device (SQUID) stack, Suzuki stack (Josephson latching driver), and nanocryotron (nTron) have a binary output that produces either a logical 0’ or 1’. Due to the limited cooling power at 4 K, a higher data rate of superconductor output driver is desired to reduce the number of cryogenic cables (i.e., heat load) from 4 K to a higher temperature stage. In this paper, a novel ternary digital output data link is proposed by transmitting the data in three logical states such as 0’, 1’, and 2’. The proposed ternary data link consists of an encoder and a ternary superconductor output driver, which is based on a re-designed Suzuki stack circuit. As compared to a conventional (binary) output data link, the ternary data link can either increase the data rate by 50% or reduce the number of cryogenic cables by33%.
Amplification of SFQ pulses to higher signal levels has been achieved using the general technique of inductive isolation. A multiple-flux-quantum generator, which produces quantum-accurate waveforms suitable for ADC applications, and an output data link were demonstrated. Both circuits were implemented using critically damped, dc-powered SQUIDs stacked in series. In the past, the voltage output achievable with this approach has been severely limited by parasitic capacitance to ground and to the control lines. Parasitic capacitance inhibits SQUID operation both at turn-on and turn-off. Using inductive isolation between SQUIDs, parasitic capacitance was completely tuned out. A 100-flux-quantum waveform generator, based on a series stack of 100 SQUIDs, operated at 6 Gb/s, fabricated in a 4.5 kA-per-square-cm Josephson junction process. The output amplifier produced a 1 mV swing at 12 Gb/s non-return-to-zero. This circuit is based on a stack of only two SQUIDs, and uses both inductive isolation and asymmetric resistive shunting to enhance the out-of-phase oscillation mode.