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IEEE Transactions on Applied Superconductivity

Energy Efficient Digital Data Link

Prasana Ravindran, Su-Wei Chang, Wei-Ting Wong, Saad M. Sarwana, Vladimir Valentinovich Dotsenko, Jia Tang, Steven Ruotolo, Deepnarayan Gupta, Joseph C. Bardin

Published Dec 7, 2016• 7 citations
Publisher

Abstract

Efficiently amplifying the high-speed and low-voltage swing outputs of single flux quantum (SFQ) logic to levels that are suitable for interfacing with room temperature electronics has been a long-standing challenge in the field of superconducting electronics. In this work, we investigate the feasibility of using a lossy passive matching network at 4 K, with a pair of differential 100 low-noise amplifiers heatsunk to 18 K and 50 K stages, respectively. The amplifiers were implemented in a 120 nm SiGe BiCMOS technology. The amplification chain is dc coupled and the small-signal link gain was measured to be approximately 48 dB. The power consumption of each of the two amplification stages was 6.3 mW. The chain was measured at 21 K using a high-speed differential nonreturn-to-zero signal having amplitude commensurate with what one would expect from a superconducting circuit, and clean eye diagrams were observed for data rates as high as 30 Gb/s. The chain was also measured when driven from an SFQ/dc interface, with the first gain stage heatsunk to 9 K. In this configuration, clean eye diagrams were observed to 5 Gb/s, with the speed limitation being related to packaging parasitics.

DOI
10.1109/tasc.2016.2636252

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Efficiently amplifying the high-speed and low-voltage swing outputs of single flux quantum (SFQ) logic to levels that are suitable for interfacing with room temperature electronics has been a long-standing challenge in the field of superconducting electronics. In this work, we investigate the feasibility of using a lossy passive matching network at 4 K, with a pair of differential 100 low-noise amplifiers heatsunk to 18 K and 50 K stages, respectively. The amplifiers were implemented in a 120 nm SiGe BiCMOS technology. The amplification chain is dc coupled and the small-signal link gain was measured to be approximately 48 dB. The power consumption of each of the two amplification stages was 6.3 mW. The chain was measured at 21 K using a high-speed differential nonreturn-to-zero signal having amplitude commensurate with what one would expect from a superconducting circuit, and clean eye diagrams were observed for data rates as high as 30 Gb/s. The chain was also measured when driven from an SFQ/dc interface, with the first gain stage heatsunk to 9 K. In this configuration, clean eye diagrams were observed to 5 Gb/s, with the speed limitation being related to packaging parasitics.
We have developed and tested simple and inexpensive electronics for interfacing Rapid Single-Flux-Quantum (RSFQ) Josephson-junction circuits to room temperature digital systems. Voltage-level (Non-Return-to-Zero) bit signals with a swing of /spl sim/150 uV, developed on-chip by standard SFQ/DC converters, and in some cases amplified to 1.5 mV swing by HUFFLE-type circuits, are passed to the 300 K environment using a high density (40 channel) flexible coplanar waveguide assembly. AC-coupled, 2-3 stage microwave Si-bipolar amps, and Emitter-Coupled-Logic (ECL) buffers accomplish voltage level translation to the standard ECL levels, Using this technique, data rates in excess of 1 Gb/s per channel can be achieved at low cost per channel,.>
High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual-JcJ_{c}Jc​(4.5 and 20kA/cm2\hbox{kA/cm}^{2}kA/cm2) fabrication process.
Superconducting computers can be realized using a Josephson-CMOS hybrid structure, combining the high speed and low power of single-flux quantum (SFQ) logic with the high integration density of CMOS technology. However, reliable interconnection between SFQ and CMOS circuits at cryogenic temperatures remains challenging due to low signal-to-noise ratio (SNR) and interference. To address these challenges, we propose a DC-biased SiGe BiCMOS interface that converts the 0.2 mV output of the SFQ/DC converter (Q2D) to 1.2 V for CMOS memory. A high-impedance voltage amplifier (VA) and a low-impedance transimpedance amplifier (TIA) were designed to optimize signal matching with the Q2D. The interfaces were simulated, fabricated, and tested at 4.2 K to evaluate their performance. Both analytical and experimental results demonstrate that the TIA significantly improves the SNR and enhances noise immunity during static random-access memory (SRAM) read/write operations, making it more effective than the VA for signal matching between the Q2D and CMOS circuits. This work presents a practcal solution for SFQ-CMOS interconnection, effectively addressing SNR and interference challenges and contributing to the development of scalable superconducting computing systems.
In a superconductor digital-RF transmitter, the power amplifier chain can be implemented in hybrid temperature, hybrid technology environment, where the superconductor switching amplifier forms the first stage of the amplification chain. We have designed several flavors of SQUID based switching amplifiers, each targeted for different power output and speed. One of the amplifiers is a differential amplifier featuring dynamic equalization. To minimize the intersymbol interference, the amplifier employs a pre-emphasis technique, thereby compensating for the bandwidth limitations of the channel. The differential output voltage of this amplifier is 16 mV at low speed (200 Mbps), which rolls off to 2 mV at 16 Gbps data rate, for an “1100” pattern (no consecutive transitions on the input data sequence). For high speed operation of the SQUID amplifiers, simultaneous switching of SQUIDs is desired to reduce the output rise and fall times. Hence, in another amplifier design, called the Differential H-Tree Amplifier, the SQUIDs are arranged in an “H-tree” structure, to equalize the propagation delay of the control signal to each SQUID. The amplifier's differential output voltage is 8 mV at low speed (200 Mbps), and rolls off to 2 mV at 10 Gbps data rate. A third type of amplifier is a differential SFQ-to-DC amplifier; it consists of a pair of synchronously driven SFQ-to-DC converters that produce complementary positive and negative voltage waveforms respectively. The differential output voltage of this amplifier is 0.8 mV, and it can be operated at very high speeds. Moreover, the complexity of this amplifier enables it to be yielded in higher critical current density process. Both, the speed and the output voltage scale as the square root of the process critical current density.
Improving the efficiency in digital data transport, originating from 4 K superconductor integrated circuits (ICs) to standard room-temperature (300 K) electronics, both in terms of speed and power consumption, is vitally important for nearly all applications of superconductor digital electronics. The required data link must include all necessary amplification and conditioning to convert digital data from single flux quantum (SFQ) logic to standard CMOS logic levels. Therefore, one must minimize the overall power consumption for the required total data throughout by taking into account all parts of the link: (1) data transmitters or output drivers with SFQ input, (2) additional amplifiers, (3) transmission lines, and (4) data receivers at room-temperature, such as the ones available on commercial field-programmable gate arrays (FPGAs). Here, we describe two variants of electrical data links, with and without cryogenic semiconductor amplifiers.
Abstract The many advantages of cryogenically cooled single-flux quantum (SFQ) circuits imply that the high speed and low voltage output signals must be amplified and interfaced with standard electronics. State-of-the-art low-noise and wide-band amplifiers are required to interface with room temperature electronics. One solution is to place preamplifiers at the cryogenic stage, which requires specific semiconductor design and fabrication. However, a more viable and energy-efficient approach is to integrate the pulsed logic circuit output stages with on-chip superconductor preamplifiers. We designed, fabricated, and tested an on-chip compact voltage multiplier integrated with the output stage of SFQ circuits to increase the voltage amplitude of SFQ pulses. The circuit is designed with the same technology as the logic circuit hence its noise level is lower, and it works at higher frequencies compared to complementary metal-oxide semi-conductor amplifiers and due to quantized nature of it there is no added noise. The fabricated circuit has a compact size of 160 µ m × 320 µ m and provides about 10 dB gain with measured 600 µ V output voltage at frequencies up to ∼25 GHz in simulations. By stacking more levels, over 20 dB gain at circuit level is achievable as shown in simulations. Moreover the gain of the superconductor voltage amplifier is quantized and programmable.