Low-Power High-Speed Hybrid Temperature Heterogeneous Technology Digital Data Link
Deepnarayan Gupta, Joseph C. Bardin, Amol Inamdar, Aniruddha Dayalu, Saad M. Sarwana, Prasana Ravindran, Su-Wei Chang, Ahmet H. Coskun, Mohammad Ghadiri-Sadrabadi
High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual-$J_{c}$(4.5 and 20$\hbox{kA/cm}^{2}$) fabrication process.
High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual-Jc(4.5 and 20kA/cm2) fabrication process.
Improving the efficiency in digital data transport, originating from 4 K superconductor integrated circuits (ICs) to standard room-temperature (300 K) electronics, both in terms of speed and power consumption, is vitally important for nearly all applications of superconductor digital electronics. The required data link must include all necessary amplification and conditioning to convert digital data from single flux quantum (SFQ) logic to standard CMOS logic levels. Therefore, one must minimize the overall power consumption for the required total data throughout by taking into account all parts of the link: (1) data transmitters or output drivers with SFQ input, (2) additional amplifiers, (3) transmission lines, and (4) data receivers at room-temperature, such as the ones available on commercial field-programmable gate arrays (FPGAs). Here, we describe two variants of electrical data links, with and without cryogenic semiconductor amplifiers.
Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10-12. We will discuss the trade-off among circuit robustness, speed, and power consumption.
We develop an energy efficient digital data link connecting cryogenic superconducting single flux quantum (SFQ) circuits to room-temperature electronics. The design is based on low-temperature (4 K) superconductor ERSFQ SFQ/dc drivers, high-temperature superconductor data cables spanning 4 K to 70 K temperature stages, mid-temperature (70 K) polarization modulation vertical cavity surface emitting lasers (PM VCSELs), and fiber optic links to room temperature electronics. The Energy-efficient Cryogenic Optical (ECO) data link design is based on balancing power dissipation and signal gain at each temperature stage to maximize overall energy efficiency following the recently introduced Thermo-Gain Rule. To achieve VCSEL light emission with two switchable distinct polarization modes, a cruciform-shaped anisotropic optical cavity is formed by fabrication of a photonic crystal with etched periodic air holes surrounding the unetched cruciform region. In this report, we present the results of design, fabrication, and preliminary testing of the ECO data link components.
Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.
Efficiently amplifying the high-speed and low-voltage swing outputs of single flux quantum (SFQ) logic to levels that are suitable for interfacing with room temperature electronics has been a long-standing challenge in the field of superconducting electronics. In this work, we investigate the feasibility of using a lossy passive matching network at 4 K, with a pair of differential 100 low-noise amplifiers heatsunk to 18 K and 50 K stages, respectively. The amplifiers were implemented in a 120 nm SiGe BiCMOS technology. The amplification chain is dc coupled and the small-signal link gain was measured to be approximately 48 dB. The power consumption of each of the two amplification stages was 6.3 mW. The chain was measured at 21 K using a high-speed differential nonreturn-to-zero signal having amplitude commensurate with what one would expect from a superconducting circuit, and clean eye diagrams were observed for data rates as high as 30 Gb/s. The chain was also measured when driven from an SFQ/dc interface, with the first gain stage heatsunk to 9 K. In this configuration, clean eye diagrams were observed to 5 Gb/s, with the speed limitation being related to packaging parasitics.
Superconductive electronics offers a unique combination of high bandwidth and low power for mission critical hardware such as digital processors at 20 to 100 GHz, microwatt per bit analog to digital converters, large digital switches at multi-Gb/s data rates, and low noise parametric amplifiers. This cryogenic technology, typically operating at a few degrees or a few tens of degrees Kelvin, depends upon the unique physics of superconducting materials such as Nb, NbN, and YBaCuO, and the fundamental circuit element, the Josephson junction (JJ) to create unique architectures of unprecedented design efficiency and performance. These circuits are based on the single flux quantum (SFQ) logic family, a technology that has no parallel in semiconductor electronics. Digital data is transmitted by voltage pulses with amplitude less than 1 mV, but at extremely high speeds. Individual gates have been operated as high as 370 GHz. In this paper, we present a brief overview of superconductive digital technology, describe some recent circuits, and discuss how the challenges to superconductive technology are being met, including the use of multi-chip module (MCM) technology, and the potential use of III-V HBT and HEMT circuits to provide interface drivers and amplifiers, possibly operated cryogenically.