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IEEE International Superconductive Electronics Conference (ISEC)

Development of Energy-efficient Cryogenic Optical (ECO) data link

Oleg A. Mukhanov, I. V. Vernik, Alex F. Kirichenko, Alan M. Kadin, Kent D. Choquette, Mingxin Tan, T M Fryslie Stewart

Published Jul 1, 2013• 3 citations
Publisher

Abstract

We develop an energy efficient digital data link connecting cryogenic superconducting single flux quantum (SFQ) circuits to room-temperature electronics. The design is based on low-temperature (4 K) superconductor ERSFQ SFQ/dc drivers, high-temperature superconductor data cables spanning 4 K to 70 K temperature stages, mid-temperature (70 K) polarization modulation vertical cavity surface emitting lasers (PM VCSELs), and fiber optic links to room temperature electronics. The Energy-efficient Cryogenic Optical (ECO) data link design is based on balancing power dissipation and signal gain at each temperature stage to maximize overall energy efficiency following the recently introduced Thermo-Gain Rule. To achieve VCSEL light emission with two switchable distinct polarization modes, a cruciform-shaped anisotropic optical cavity is formed by fabrication of a photonic crystal with etched periodic air holes surrounding the unetched cruciform region. In this report, we present the results of design, fabrication, and preliminary testing of the ECO data link components.

DOI
10.1109/isec.2013.6604276

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We develop an energy efficient digital data link connecting cryogenic superconducting single flux quantum (SFQ) circuits to room-temperature electronics. The design is based on low-temperature (4 K) superconductor ERSFQ SFQ/dc drivers, high-temperature superconductor data cables spanning 4 K to 70 K temperature stages, mid-temperature (70 K) polarization modulation vertical cavity surface emitting lasers (PM VCSELs), and fiber optic links to room temperature electronics. The Energy-efficient Cryogenic Optical (ECO) data link design is based on balancing power dissipation and signal gain at each temperature stage to maximize overall energy efficiency following the recently introduced Thermo-Gain Rule. To achieve VCSEL light emission with two switchable distinct polarization modes, a cruciform-shaped anisotropic optical cavity is formed by fabrication of a photonic crystal with etched periodic air holes surrounding the unetched cruciform region. In this report, we present the results of design, fabrication, and preliminary testing of the ECO data link components.
High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual-JcJ_{c}Jc​(4.5 and 20kA/cm2\hbox{kA/cm}^{2}kA/cm2) fabrication process.
Improving the efficiency in digital data transport, originating from 4 K superconductor integrated circuits (ICs) to standard room-temperature (300 K) electronics, both in terms of speed and power consumption, is vitally important for nearly all applications of superconductor digital electronics. The required data link must include all necessary amplification and conditioning to convert digital data from single flux quantum (SFQ) logic to standard CMOS logic levels. Therefore, one must minimize the overall power consumption for the required total data throughout by taking into account all parts of the link: (1) data transmitters or output drivers with SFQ input, (2) additional amplifiers, (3) transmission lines, and (4) data receivers at room-temperature, such as the ones available on commercial field-programmable gate arrays (FPGAs). Here, we describe two variants of electrical data links, with and without cryogenic semiconductor amplifiers.
Superconducting processor based on single flux quantum (SFQ) technology is a promising solution for cryogenic computing with high-speed operation at extremely low power. However, energy-efficient data link from∼4K\sim 4\text{K}∼4Koperation to room temperature (RT) users has been remained as a key challenger to be resolved. In this work, we report the 5K performance of 51.56 Gb/s PAM-4 optical data link from a VCSEL, coupled by free-space optics inside cryostat to RT receiver through cryostat optical window. Finally, a superconducting bit pattern generator (BPG) is used to modulate a VCSEL at 4 K: 12.5 Gb/s NRZ error-free optical data transmission and 20 Gb/s NRZ open eye-diagrams are demonstrated via an OM4 fiber coupled directly to the VCSEL at 4 K inside cryostat and linked to the outside receiver at RT.
Data transmission from single flux quantum (SFQ) circuits to room temperature electronics requires the use of superconductor output drivers and semiconductor amplifiers. The state-of-the-art superconductor output drivers such as SFQ-to-DC converter, superconducting quantum interference device (SQUID) stack, Suzuki stack (Josephson latching driver), and nanocryotron (nTron) have a binary output that produces either a logical 0’ or 1’. Due to the limited cooling power at 4 K, a higher data rate of superconductor output driver is desired to reduce the number of cryogenic cables (i.e., heat load) from 4 K to a higher temperature stage. In this paper, a novel ternary digital output data link is proposed by transmitting the data in three logical states such as 0’, 1’, and 2’. The proposed ternary data link consists of an encoder and a ternary superconductor output driver, which is based on a re-designed Suzuki stack circuit. As compared to a conventional (binary) output data link, the ternary data link can either increase the data rate by 50% or reduce the number of cryogenic cables by33%.
Cryogenic systems necessitate extensive data transmission between room-temperature and cryogenic environments, as well as within the cryogenic temperature domain. High-speed, low-power data transmission is pivotal to enabling the deployment of larger-scale cryogenic systems, including the scalable quantum computing systems and the high-performance cryogenic computing systems fully immersed in liquid nitrogen. In contrast to wireline and microwave links, optical communication links are emerging as a solution characterized by high data rates, high energy efficiency, low signal attenuation, absence of thermal conduction, and superior scalability. In this work, a 4K heat-insulated high-speed (56Gbps) low-power (1.6pJ/b) transceiver (TRX) that achieves a complete link between 4K systems and room temperature (RT) equipment is presented. Copackaged with a PIN photodiode (PD), the RX uses an inverter-based analog front-end and an analog half-rate clock data recovery loop. Connecting to a Mach-Zehnder modulator (MZM), the TX contains a voltage-mode driver with current-mode injection for low-power output-swing-boosting and 3-tap feed-forward equalization (FFE). This link has been demonstrated in the control and readout of a complete superconducting quantum computing system.
In recent years, standard CMOS microprocessors have approached their maximum power dissipation per unit area, effectively placing a limit on computational power. This highlights the urgent need to explore alternative technologies. One promising avenue is the use of superconductors, which demonstrate zero resistivity below a critical temperature. However, circuits based on superconductors necessitate the use of cryostats to maintain low temperatures, presenting challenges in data transfer with the room temperature environment. While coaxial cables are often employed for this purpose, they suffer from limited data transfer rates and contribute significantly to heat load. On the contrary, photonics integrated circuits (PICs) coupled with optical fibers present a viable solution. They enable scalable, cost-effective, and power-efficient optical interconnections capable of supporting high data transfer rates while minimizing heat transfer. In this presentation, We will discuss the latest advancements in cryogenic PICs, focusing on their application in interfacing with cryogenic computing systems such as single-flux-quantum logic circuits and superconducting qubits.