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IEEE Transactions on Applied Superconductivity

Ternary Digital Output Data Link From SFQ Circuits

Yerzhan Mustafa, Selçuk Köse

Published Dec 2, 2024• 5 citations
Publisher

Abstract

Data transmission from single flux quantum (SFQ) circuits to room temperature electronics requires the use of superconductor output drivers and semiconductor amplifiers. The state-of-the-art superconductor output drivers such as SFQ-to-DC converter, superconducting quantum interference device (SQUID) stack, Suzuki stack (Josephson latching driver), and nanocryotron (nTron) have a binary output that produces either a logical 0’ or 1’. Due to the limited cooling power at 4 K, a higher data rate of superconductor output driver is desired to reduce the number of cryogenic cables (i.e., heat load) from 4 K to a higher temperature stage. In this paper, a novel ternary digital output data link is proposed by transmitting the data in three logical states such as 0’, 1’, and 2’. The proposed ternary data link consists of an encoder and a ternary superconductor output driver, which is based on a re-designed Suzuki stack circuit. As compared to a conventional (binary) output data link, the ternary data link can either increase the data rate by 50% or reduce the number of cryogenic cables by33%.

DOI
10.1109/tasc.2024.3510520

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Data transmission from single flux quantum (SFQ) circuits to room temperature electronics requires the use of superconductor output drivers and semiconductor amplifiers. The state-of-the-art superconductor output drivers such as SFQ-to-DC converter, superconducting quantum interference device (SQUID) stack, Suzuki stack (Josephson latching driver), and nanocryotron (nTron) have a binary output that produces either a logical 0’ or 1’. Due to the limited cooling power at 4 K, a higher data rate of superconductor output driver is desired to reduce the number of cryogenic cables (i.e., heat load) from 4 K to a higher temperature stage. In this paper, a novel ternary digital output data link is proposed by transmitting the data in three logical states such as 0’, 1’, and 2’. The proposed ternary data link consists of an encoder and a ternary superconductor output driver, which is based on a re-designed Suzuki stack circuit. As compared to a conventional (binary) output data link, the ternary data link can either increase the data rate by 50% or reduce the number of cryogenic cables by33%.
Improving the efficiency in digital data transport, originating from 4 K superconductor integrated circuits (ICs) to standard room-temperature (300 K) electronics, both in terms of speed and power consumption, is vitally important for nearly all applications of superconductor digital electronics. The required data link must include all necessary amplification and conditioning to convert digital data from single flux quantum (SFQ) logic to standard CMOS logic levels. Therefore, one must minimize the overall power consumption for the required total data throughout by taking into account all parts of the link: (1) data transmitters or output drivers with SFQ input, (2) additional amplifiers, (3) transmission lines, and (4) data receivers at room-temperature, such as the ones available on commercial field-programmable gate arrays (FPGAs). Here, we describe two variants of electrical data links, with and without cryogenic semiconductor amplifiers.
Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.
Superconductor-semiconductor interface circuits are integral part of connecting cryogenic classical and quantum computing systems with the room temperature electronics. Due to the cooling power constraints of cryogenic setups, the number of data transmission channels between temperature stages is often limited by the heat load of cables and connectors. As a result, a high data rate (throughput) per channel is desired for large-scale computing systems. The state-of-the-art superconductor-semiconductor interface circuits use a binary data format. In this work, a novel interface circuit is proposed that produces signals with pulse-amplitude modulation (PAM). As a case study, a PAM-4 SQUID (superconducting quantum interference device) stack interface circuit is developed. With four output voltage levels, the effective data rate can be doubled while keeping the same operating frequency. Alternatively, the number of cryogenic cables can be reduced by two times as compared to the conventional binary data links.
High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual-JcJ_{c}Jc​(4.5 and 20kA/cm2\hbox{kA/cm}^{2}kA/cm2) fabrication process.
Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10-12. We will discuss the trade-off among circuit robustness, speed, and power consumption.
We develop an energy efficient digital data link connecting cryogenic superconducting single flux quantum (SFQ) circuits to room-temperature electronics. The design is based on low-temperature (4 K) superconductor ERSFQ SFQ/dc drivers, high-temperature superconductor data cables spanning 4 K to 70 K temperature stages, mid-temperature (70 K) polarization modulation vertical cavity surface emitting lasers (PM VCSELs), and fiber optic links to room temperature electronics. The Energy-efficient Cryogenic Optical (ECO) data link design is based on balancing power dissipation and signal gain at each temperature stage to maximize overall energy efficiency following the recently introduced Thermo-Gain Rule. To achieve VCSEL light emission with two switchable distinct polarization modes, a cruciform-shaped anisotropic optical cavity is formed by fabrication of a photonic crystal with etched periodic air holes surrounding the unetched cruciform region. In this report, we present the results of design, fabrication, and preliminary testing of the ECO data link components.