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IEEE Transactions on Applied Superconductivity

Measurement of Superconductive Voltage Drivers up to 25 Gb/s/ch

Y. Hashimoto, Hideo Suzuki, Shuichi Nagasawa, Michitaka Maruyama, K. Fujiwara, Mutsuo Hidaka

Published May 27, 2009• 10 citations

Abstract

We report on demonstrations of a superconductive voltage driver (SVD), which generates non-return-to-zero (NRZ) output with an SFQ pulse input, up to 25 Gb/s/ch. The NRZ SVD consists of a coding logic, splitters, buffers, sixteen RS flip-flops (RSFFs), and DC-biased serially connected sixteen 2-junction SQUIDs. Each SQUID is magnetically coupled to the storage loop of each RSFF. The coding logic generates the true and complement signals of the SVD's input data, and the true and complement signals are split into sixteen with the splitters, amplified with the buffers, and applied to the RSFFs as the set and reset signals, respectively. With this configuration, the SQUIDs generate about 2-mV-high NRZ output voltage. The NRZ SVD was fabricated with our 10-kA/cm2Nb process and measured with our cryocooled system. Eye diagram of the NRZ SVD measured at 25 Gb/s/ch clearly opened, indicating low-bit-error-rate (BER) operation. Measured BER was less than 1times10-13at 20 Gb/s/ch for 27-1 pseudo-random bit sequence input.

DOI: 10.1109/tasc.2009.2017867

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High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.

We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.

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We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RSFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gb/s for a (2/sup 31/-1) bit long pseudo-random bit sequence (PRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.

A new Josephson latching driver with a current-injection device at an input port has been developed and tested. It has high input sensitivity and a wide bias margin. Under an optimal bias condition, the bit-error rate (BER) of this driver is below 10/sup -12/ at data rates of 5 and 10 Gb/s. The driver can be switched by superconducting single-flux quantum (SFQ) pulse input and can be used as an amplifier to test the BER of SFQ circuits. In such a test, the BER of an SFQ converter operating at 5 Gb/s was less than 10/sup -12/ with bias margin of /spl plusmn/20%.