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Superconductor Science and Technology

Design and characterization of adiabatic quantum flux parametron using sub- μ m cross-type Josephson junction technology

S G Reddy, Matthias Schmelz, J. Kunert, T Ortlepp, G. Oelsner, Hannes Toepfer, Ronny Stolz

Published Mar 5, 2025• 1 citation
Publisher

Abstract

Abstract We report on the design and implementation of adiabatic quantum flux parametron (AQFP) buffer gates utilizing cross-type Nb/AlO x /Nb Josephson junctions with I C of 20 μ A, designed to operate at mK temperatures. We, therefore, discuss design considerations, circuit simulation and optimization and their technological implementation. The preliminary results of the test circuit at 4.2 K are demonstrated focusing on the performance. Particularly, we emphasize on the current sensitivity of the circuit based on the output switching probability. The measurement results, show a narrow grayzone width of 0.48 μ A for low-speed operation, demonstrating a higher current sensitivity. Additionally, the designed AQFP circuit exhibits a wide operating margins, further endorsing their potential for high sensitivity based superconducting sensors and scalable interface circuits for quantum electronics.

DOI
10.1088/1361-6668/adbce0

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Scientific Reports•Nov 21, 2025•3 citations
Abstract We report on the design and implementation of adiabatic quantum flux parametron (AQFP) buffer gates utilizing cross-type Nb/AlO x /Nb Josephson junctions with I C of 20 μ A, designed to operate at mK temperatures. We, therefore, discuss design considerations, circuit simulation and optimization and their technological implementation. The preliminary results of the test circuit at 4.2 K are demonstrated focusing on the performance. Particularly, we emphasize on the current sensitivity of the circuit based on the output switching probability. The measurement results, show a narrow grayzone width of 0.48 μ A for low-speed operation, demonstrating a higher current sensitivity. Additionally, the designed AQFP circuit exhibits a wide operating margins, further endorsing their potential for high sensitivity based superconducting sensors and scalable interface circuits for quantum electronics.
Abstract Adiabatic quantum-flux-parametron (AQFP) is an adiabatic logic based on the quantum-flux-parametron. It has extremely low switching energy, as well as high signal gain and high robustness. In this work, we present the development of an AQFP cell library using the MIT LL 100 μ A μ m −2 superconductor electronics fabrication process, SFQ5ee. Four types of basic sub-cells, i.e. buffer, inverter, constant, and branch, are designed as the building blocks for combinational AQFP logic cells. Taking advantage of the 8 metal layers, we place the dc superconducting quantum interference device (SQUID) part of a buffer above the ground plane and the signal transformer part below the ground plane to mitigate unwanted couplings. In addition, by vertically overlapping the signal transformer and the dc SQUID, the dimension of a buffer is reduced to 15 μ m × 20 μ m, which is only 30% of that of the conventional design. More complex AQFP logic cells, such as the majority gate, AND gate, and OR gate, are designed by arraying the sub-cells together. Correct operations and wide excitation current margins are confirmed for the established AQFP logic cells by both simulation and experiments.
Abstract We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm −2 Nb high-speed standard process as well as the AIST 2.5 kA cm −2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14–37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.
Adiabatic quantum-flux-parametron (AQFP) superconductor logic is a proven energy-efficient digital technology for various applications. To address the scalability challenges of this technology, we investigated AQFP shift registers with the AQFP footprint area reduced by 25% with respect to prior work and with the >2× denser overall circuit designs obtained by eliminating the previously used free space between the AQFPs. We also investigated AQFP cells with different designs of flux trapping moats in the superconducting ground plane as well as compact AQFP cells that took advantage of the smaller feature sizes available in the new fabrication process, SFQ5ee+, at MIT Lincoln Laboratory (MIT LL). This new process features nine planarized Nb layers with a 0.25 μm minimum linewidth. The fabricated circuits were tested in a liquid He immersion probe and a commercial closed-cycle cryocooler using a controlled cooling rate through the superconducting critical temperature,Tc. Using multiple thermal cycles, we investigated flux trapping in the dense AQFP shift registers as well as in the registers using the old (sparse) AQFP designs at two levels of the residual magnetic field, about 0.53 μT and about 1.2 μT. The sparse designs demonstrated 95% to almost 100% probability of operation after the cooldown and very wide operation margins, although the flux trapping probability was increasing with circuit complexities. The margins were similarly wide in the newer dense designs, but flux trapping probability that rendered the registers nonoperational was significantly, by an order of magnitude, higher in these denser circuits and was also very sensitive to the moats' shape and location. Our findings indicate that AQFP circuits are amendable to increasing the scale of integration and further densification, but a careful moat design and optimization are required to reduce flux trapping effects in the dense AQFP circuits.
We have been investigating an ultra-low-power adiabatic quantum-flux-parametron (AQFP) logic, the energy dissipation of which can be decreased by changing its potential energy slowly or adiabatically. In the present study, we designed basic AQFP logic gates and an AQFP 1-bit full adder, and examined their operations through simulations and experiments. The AQFP 1-bit full adder is composed of 46 Josephson junctions, which is approximately one-quarter the number of junctions of a full adder using conventional rapid single-flux-quantum logic. The measurement results indicated that the AQFP 1-bit full adder has a wide current bias margin of as large as ±27.8%.
We investigated interface circuits between rapid single-flux-quantum (RSFQ) circuits and adiabatic quantum-flux-parametron (AQFP) circuits for a high-speed and low-power hybrid computing system. In addition, the interface circuits allow us to use long-distance interconnections based on single-flux-quantum (SFQ) passive transmission lines between AQFP gates. The target frequency of interface circuits is several gigahertz. There are two types of interface circuits. The RSFQ/AQFP interface circuit, which transmits a signal from RSFQ circuits to AQFP gates, was realized by coupling an RSFQ toggle flip-flop (TFF) to an AQFP buffer gate. The simulated bias margins of the RSFQ TFF and the excitation current margin of the RSFQ/AQFP interface were 2.22 mA ± 24.7% and 1.71 mA ± 25.0%, respectively. The AQFP/RSFQ interface circuit, which transmits a signal from AQFP gates to RSFQ circuits, was designed by using a high-sensitive magnetically coupled dc/SFQ converter (MC-dc/SFQ) to detect an output current of an AQFP buffer gate. The simulated bias margins of the MC-dc/SFQ and the excitation current margin of the AQFP/RSFQ interface were 0.558 mA ± 20.5% and 1.95 mA ± 36.1%, respectively. We also fabricated and measured the interface circuits.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.